diff --exclude=CVS --exclude='.#*' --exclude='obj.*' --exclude='makeBuild*' -uNr src.orig/sys/dev/usb/files.usb src/sys/dev/usb/files.usb --- src.orig/sys/dev/usb/files.usb 2012-01-17 12:49:20.000000000 +0900 +++ src/sys/dev/usb/files.usb 2012-01-19 23:01:28.000000000 +0900 @@ -410,3 +410,8 @@ device urndis: arp, ether, ifnet attach urndis at usbifif file dev/usb/if_urndis.c urndis + +# Realtek RTL8188CU/RTL8192CU +device urtwn: ether, ifnet, arp, wlan, firmload +attach urtwn at usbdevif +file dev/usb/if_urtwn.c urtwn diff --exclude=CVS --exclude='.#*' --exclude='obj.*' --exclude='makeBuild*' -uNr src.orig/sys/dev/usb/if_urtwn.c src/sys/dev/usb/if_urtwn.c --- src.orig/sys/dev/usb/if_urtwn.c 1970-01-01 09:00:00.000000000 +0900 +++ src/sys/dev/usb/if_urtwn.c 2012-01-30 21:34:20.000000000 +0900 @@ -0,0 +1,3523 @@ +/* $NetBSD$ */ +/* $OpenBSD: if_urtwn.c,v 1.20 2011/11/26 06:39:33 ckuethe Exp $ */ + +/*- + * Copyright (c) 2010 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/*- + * Copyright (C) 2012 NONAKA Kimihiro + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU. + */ + +#include +__KERNEL_RCSID(0, "$NetBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef USB_DEBUG +#define URTWN_DEBUG +#endif + +#ifdef URTWN_DEBUG +#define DPRINTFN(n, s) do { if (urtwn_debug & (n)) printf s; } while (0) +#define DBG_INIT __BIT(0) +#define DBG_FN __BIT(1) +#define DBG_TX __BIT(2) +#define DBG_RX __BIT(3) +#define DBG_STM __BIT(4) +#define DBG_RF __BIT(5) +#define DBG_ALL 0xffffffffU +u_int urtwn_debug = DBG_TX|DBG_RX|DBG_STM; +#else +#define DPRINTFN(n, s) +#endif + +static const struct usb_devno urtwn_devs[] = { + { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_1 }, + { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_2 }, + { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8192CU }, + { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_1 }, + { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_2 }, + { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8188CU }, + { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192CU }, + { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8188CU }, + { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_1 }, + { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_2 }, + { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_3 }, + { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8188CU }, + { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192CU }, + { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8188CU }, + { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8192CU }, + { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUP150 }, + { USB_VENDOR_HP3, USB_PRODUCT_HP3_RTL8188CU }, + { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000M }, + { USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_RTL8188CU }, + { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_1 }, + { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_2 }, + { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8192CU }, + { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_0 }, + { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_1 }, + { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_0 }, + { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_1 }, + { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_2 }, + { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU }, + { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8191CU }, + { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CE }, + { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CU }, + { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU }, + { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8188CU }, + { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_RTL8192CU } +}; + +static int urtwn_match(device_t, cfdata_t, void *); +static void urtwn_attach(device_t, device_t, void *); +static int urtwn_detach(device_t, int); +static int urtwn_activate(device_t, enum devact); + +CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, + urtwn_attach, urtwn_detach, urtwn_activate); + +static int urtwn_open_pipes(struct urtwn_softc *); +static void urtwn_close_pipes(struct urtwn_softc *); +static int urtwn_alloc_rx_list(struct urtwn_softc *); +static void urtwn_free_rx_list(struct urtwn_softc *); +static int urtwn_alloc_tx_list(struct urtwn_softc *); +static void urtwn_free_tx_list(struct urtwn_softc *); +static void urtwn_task(void *); +static void urtwn_do_async(struct urtwn_softc *, + void (*)(struct urtwn_softc *, void *), void *, int); +static void urtwn_wait_async(struct urtwn_softc *); +static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, + int); +static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, + int); +static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); +static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); +static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); +static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); +static void urtwn_efuse_read(struct urtwn_softc *); +static int urtwn_read_chipid(struct urtwn_softc *); +static void urtwn_read_rom(struct urtwn_softc *); +static int urtwn_media_change(struct ifnet *); +static int urtwn_ra_init(struct urtwn_softc *); +static void urtwn_tsf_sync_enable(struct urtwn_softc *); +static void urtwn_set_led(struct urtwn_softc *, int, int); +static void urtwn_calib_to(void *); +static void urtwn_calib_to_cb(struct urtwn_softc *, void *); +static void urtwn_next_scan(void *); +static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, + int); +static void urtwn_newstate_cb(struct urtwn_softc *, void *); +static int urtwn_wme_update(struct ieee80211com *); +static void urtwn_wme_update_cb(struct urtwn_softc *, void *); +static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); +static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); +static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); +static void urtwn_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status); +static void urtwn_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status); +static int urtwn_tx(struct urtwn_softc *, struct mbuf *, + struct ieee80211_node *); +static void urtwn_start(struct ifnet *); +static void urtwn_watchdog(struct ifnet *); +static int urtwn_ioctl(struct ifnet *, u_long, void *); +static int urtwn_power_on(struct urtwn_softc *); +static int urtwn_llt_init(struct urtwn_softc *); +static void urtwn_fw_reset(struct urtwn_softc *); +static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); +static int urtwn_load_firmware(struct urtwn_softc *); +static int urtwn_dma_init(struct urtwn_softc *); +static void urtwn_mac_init(struct urtwn_softc *); +static void urtwn_bb_init(struct urtwn_softc *); +static void urtwn_rf_init(struct urtwn_softc *); +static void urtwn_cam_init(struct urtwn_softc *); +static void urtwn_pa_bias_init(struct urtwn_softc *); +static void urtwn_rxfilter_init(struct urtwn_softc *); +static void urtwn_edca_init(struct urtwn_softc *); +static void urtwn_write_txpower(struct urtwn_softc *, int, uint16_t[]); +static void urtwn_get_txpower(struct urtwn_softc *, int, u_int, u_int, + uint16_t[]); +static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); +static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, + u_int); +static void urtwn_iq_calib(struct urtwn_softc *, bool); +static void urtwn_lc_calib(struct urtwn_softc *); +static void urtwn_temp_calib(struct urtwn_softc *); +static int urtwn_init(struct ifnet *); +static void urtwn_stop(struct ifnet *, int); + +/* Aliases. */ +#define urtwn_bb_write urtwn_write_4 +#define urtwn_bb_read urtwn_read_4 + +static int +urtwn_match(device_t parent, cfdata_t match, void *aux) +{ + struct usb_attach_arg *uaa = aux; + + return ((usb_lookup(urtwn_devs, uaa->vendor, uaa->product) != NULL) ? + UMATCH_VENDOR_PRODUCT : UMATCH_NONE); +} + +static void +urtwn_attach(device_t parent, device_t self, void *aux) +{ + struct urtwn_softc *sc = device_private(self); + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = &sc->sc_if; + struct usb_attach_arg *uaa = aux; + char *devinfop; + int i, error; + + sc->sc_dev = self; + sc->sc_udev = uaa->device; + + aprint_naive("\n"); + aprint_normal("\n"); + + devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); + aprint_normal_dev(self, "%s\n", devinfop); + usbd_devinfo_free(devinfop); + + mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); + mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NET); + mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); + + usb_init_task(&sc->sc_task, urtwn_task, sc); + + callout_init(&sc->sc_scan_to, 0); + callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); + callout_init(&sc->sc_calib_to, 0); + callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); + + if (usbd_set_config_no(sc->sc_udev, 1, 0) != 0) { + aprint_error_dev(self, "could not set configuration no\n"); + goto fail; + } + + /* Get the first interface handle. */ + error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); + if (error != 0) { + aprint_error_dev(self, "could not get interface handle\n"); + goto fail; + } + + error = urtwn_read_chipid(sc); + if (error != 0) { + aprint_error_dev(self, "unsupported test chip\n"); + goto fail; + } + + /* Determine number of Tx/Rx chains. */ + if (sc->chip & URTWN_CHIP_92C) { + sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; + sc->nrxchains = 2; + } else { + sc->ntxchains = 1; + sc->nrxchains = 1; + } + urtwn_read_rom(sc); + + aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", + (sc->chip & URTWN_CHIP_92C) ? "8192CU" : + (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : + (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : + "8188CUS", sc->ntxchains, sc->nrxchains, + ether_sprintf(ic->ic_myaddr)); + + error = urtwn_open_pipes(sc); + if (error != 0) { + aprint_error_dev(sc->sc_dev, "could not open pipes\n"); + goto fail; + } + + /* + * Setup the 802.11 device. + */ + ic->ic_ifp = ifp; + ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ + ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ + ic->ic_state = IEEE80211_S_INIT; + + /* Set device capabilities. */ + ic->ic_caps = + IEEE80211_C_MONITOR | /* Monitor mode supported. */ + IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ + IEEE80211_C_SHSLOT | /* Short slot time supported. */ + IEEE80211_C_WME | /* 802.11e */ + IEEE80211_C_WPA; /* 802.11i */ + + /* Set supported .11b and .11g rates. */ + ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; + ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; + + /* Set supported .11b and .11g channels (1 through 14). */ + for (i = 1; i <= 14; i++) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); + ic->ic_channels[i].ic_flags = + IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | + IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; + } + + ifp->if_softc = sc; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_init = urtwn_init; + ifp->if_ioctl = urtwn_ioctl; + ifp->if_start = urtwn_start; + ifp->if_watchdog = urtwn_watchdog; + IFQ_SET_READY(&ifp->if_snd); + memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); + + if_attach(ifp); + ieee80211_ifattach(ic); + /* override default methods */ + ic->ic_wme.wme_update = urtwn_wme_update; + + /* Override state transition machine. */ + sc->sc_newstate = ic->ic_newstate; + ic->ic_newstate = urtwn_newstate; + ieee80211_media_init(ic, urtwn_media_change, ieee80211_media_status); + + bpf_attach2(ifp, DLT_IEEE802_11_RADIO, + sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, + &sc->sc_drvbpf); + + sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); + sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); + sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); + + sc->sc_txtap_len = sizeof(sc->sc_txtapu); + sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); + sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); + + ieee80211_announce(ic); + + usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); + + SET(sc->sc_flags, URTWN_FLAG_ATTACHED); + return; + + fail: + sc->sc_dying = 1; + aprint_error_dev(self, "attach failed\n"); +} + +static int +urtwn_detach(device_t self, int flags) +{ + struct urtwn_softc *sc = device_private(self); + struct ifnet *ifp = &sc->sc_if; + int s; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + s = splusb(); + + sc->sc_dying = 1; + + callout_halt(&sc->sc_scan_to, NULL); + callout_halt(&sc->sc_calib_to, NULL); + + if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { + usb_rem_task(sc->sc_udev, &sc->sc_task); + urtwn_stop(ifp, 0); + + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + bpf_detach(ifp); + ieee80211_ifdetach(&sc->sc_ic); + if_detach(ifp); + + /* Abort and close Tx/Rx pipes. */ + urtwn_close_pipes(sc); + } + + splx(s); + + usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); + + callout_destroy(&sc->sc_scan_to); + callout_destroy(&sc->sc_calib_to); + mutex_destroy(&sc->sc_fwcmd_mtx); + mutex_destroy(&sc->sc_tx_mtx); + mutex_destroy(&sc->sc_task_mtx); + + return (0); +} + +static int +urtwn_activate(device_t self, enum devact act) +{ + struct urtwn_softc *sc = device_private(self); + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + switch (act) { + case DVACT_DEACTIVATE: + if_deactivate(sc->sc_ic.ic_ifp); + return (0); + default: + return (EOPNOTSUPP); + } +} + +static int +urtwn_open_pipes(struct urtwn_softc *sc) +{ + /* Bulk-out endpoints addresses (from highest to lowest prio). */ + static const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; + usb_interface_descriptor_t *id; + usb_endpoint_descriptor_t *ed; + int i, ntx = 0, error; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Determine the number of bulk-out pipes. */ + id = usbd_get_interface_descriptor(sc->sc_iface); + for (i = 0; i < id->bNumEndpoints; i++) { + ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); + if (ed != NULL && + UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && + UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) + ntx++; + } + DPRINTFN(DBG_INIT, ("%s: %s: found %d bulk-out pipes\n", + device_xname(sc->sc_dev), __func__, ntx)); + if (ntx == 0 || ntx > R92C_MAX_EPOUT) { + aprint_error_dev(sc->sc_dev, + "%d: invalid number of Tx bulk pipes\n", ntx); + return (EIO); + } + + /* Open bulk-in pipe at address 0x81. */ + error = usbd_open_pipe(sc->sc_iface, 0x81, 0, &sc->rx_pipe); + if (error != 0) { + aprint_error_dev(sc->sc_dev, "could not open Rx bulk pipe\n"); + goto fail; + } + + /* Open bulk-out pipes (up to 3). */ + for (i = 0; i < ntx; i++) { + error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0, + &sc->tx_pipe[i]); + if (error != 0) { + aprint_error_dev(sc->sc_dev, + "could not open Tx bulk pipe 0x%02x\n", epaddr[i]); + goto fail; + } + } + + /* Map 802.11 access categories to USB pipes. */ + sc->ac2idx[WME_AC_BK] = + sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); + sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; + sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ + + fail: + if (error != 0) + urtwn_close_pipes(sc); + return (error); +} + +static void +urtwn_close_pipes(struct urtwn_softc *sc) +{ + int i; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Close Rx pipe. */ + if (sc->rx_pipe != NULL) { + usbd_abort_pipe(sc->rx_pipe); + usbd_close_pipe(sc->rx_pipe); + sc->rx_pipe = NULL; + } + /* Close Tx pipes. */ + for (i = 0; i < R92C_MAX_EPOUT; i++) { + if (sc->tx_pipe[i] == NULL) + continue; + usbd_abort_pipe(sc->tx_pipe[i]); + usbd_close_pipe(sc->tx_pipe[i]); + sc->tx_pipe[i] = NULL; + } +} + +static int +urtwn_alloc_rx_list(struct urtwn_softc *sc) +{ + struct urtwn_rx_data *data; + int i, error = 0; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { + data = &sc->rx_data[i]; + + data->sc = sc; /* Backpointer for callbacks. */ + + data->xfer = usbd_alloc_xfer(sc->sc_udev); + if (data->xfer == NULL) { + aprint_error_dev(sc->sc_dev, + "could not allocate xfer\n"); + error = ENOMEM; + break; + } + + data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); + if (data->buf == NULL) { + aprint_error_dev(sc->sc_dev, + "could not allocate xfer buffer\n"); + error = ENOMEM; + break; + } + } + if (error != 0) + urtwn_free_rx_list(sc); + return (error); +} + +static void +urtwn_free_rx_list(struct urtwn_softc *sc) +{ + int i; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* NB: Caller must abort pipe first. */ + for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { + if (sc->rx_data[i].xfer != NULL) { + usbd_free_xfer(sc->rx_data[i].xfer); + sc->rx_data[i].xfer = NULL; + } + } +} + +static int +urtwn_alloc_tx_list(struct urtwn_softc *sc) +{ + struct urtwn_tx_data *data; + int i, error = 0; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + mutex_enter(&sc->sc_tx_mtx); + TAILQ_INIT(&sc->tx_free_list); + for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { + data = &sc->tx_data[i]; + + data->sc = sc; /* Backpointer for callbacks. */ + + data->xfer = usbd_alloc_xfer(sc->sc_udev); + if (data->xfer == NULL) { + aprint_error_dev(sc->sc_dev, + "could not allocate xfer\n"); + error = ENOMEM; + goto fail; + } + + data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); + if (data->buf == NULL) { + aprint_error_dev(sc->sc_dev, + "could not allocate xfer buffer\n"); + error = ENOMEM; + goto fail; + } + + /* Append this Tx buffer to our free list. */ + TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); + } + mutex_exit(&sc->sc_tx_mtx); + return (0); + + fail: + urtwn_free_tx_list(sc); + return (error); +} + +static void +urtwn_free_tx_list(struct urtwn_softc *sc) +{ + struct urtwn_tx_data *data; + int i; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* NB: Caller must abort pipe first. */ + for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { + data = &sc->tx_data[i]; + + if (data->xfer != NULL) { + usbd_free_xfer(data->xfer); + data->xfer = NULL; + } + } +} + +static void +urtwn_task(void *arg) +{ + struct urtwn_softc *sc = arg; + struct urtwn_host_cmd_ring *ring = &sc->cmdq; + struct urtwn_host_cmd *cmd; + int s; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Process host commands. */ + s = splusb(); + mutex_spin_enter(&sc->sc_task_mtx); + while (ring->next != ring->cur) { + cmd = &ring->cmd[ring->next]; + mutex_spin_exit(&sc->sc_task_mtx); + splx(s); + /* Invoke callback. */ + cmd->cb(sc, cmd->data); + s = splusb(); + mutex_spin_enter(&sc->sc_task_mtx); + ring->queued--; + ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; + } + mutex_spin_exit(&sc->sc_task_mtx); + wakeup(&sc->cmdq); + splx(s); +} + +static void +urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), + void *arg, int len) +{ + struct urtwn_host_cmd_ring *ring = &sc->cmdq; + struct urtwn_host_cmd *cmd; + int s; + + DPRINTFN(DBG_FN, ("%s: %s: cb=%p, arg=%p, len=%d\n", + device_xname(sc->sc_dev), __func__, cb, arg, len)); + + s = splusb(); + mutex_spin_enter(&sc->sc_task_mtx); + cmd = &ring->cmd[ring->cur]; + cmd->cb = cb; + KASSERT(len <= sizeof(cmd->data)); + memcpy(cmd->data, arg, len); + ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; + + /* If there is no pending command already, schedule a task. */ + if (!sc->sc_dying && ++ring->queued == 1) { + mutex_spin_exit(&sc->sc_task_mtx); + usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); + } else + mutex_spin_exit(&sc->sc_task_mtx); + splx(s); +} + +static void +urtwn_wait_async(struct urtwn_softc *sc) +{ + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Wait for all queued asynchronous commands to complete. */ + while (sc->cmdq.queued > 0) + tsleep(&sc->cmdq, 0, "endtask", 0); +} + +static int +urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, + int len) +{ + usb_device_request_t req; + + req.bmRequestType = UT_WRITE_VENDOR_DEVICE; + req.bRequest = R92C_REQ_REGS; + USETW(req.wValue, addr); + USETW(req.wIndex, 0); + USETW(req.wLength, len); + return (usbd_do_request(sc->sc_udev, &req, buf)); +} + +static __inline void +urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) +{ + + urtwn_write_region_1(sc, addr, &val, 1); +} + +static __inline void +urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) +{ + + val = htole16(val); + urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); +} + +static __inline void +urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) +{ + + val = htole32(val); + urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); +} + +static int +urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, + int len) +{ + usb_device_request_t req; + + req.bmRequestType = UT_READ_VENDOR_DEVICE; + req.bRequest = R92C_REQ_REGS; + USETW(req.wValue, addr); + USETW(req.wIndex, 0); + USETW(req.wLength, len); + return (usbd_do_request(sc->sc_udev, &req, buf)); +} + +static __inline uint8_t +urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) +{ + uint8_t val; + + if (urtwn_read_region_1(sc, addr, &val, 1) != 0) + return (0xff); + return (val); +} + +static __inline uint16_t +urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) +{ + uint16_t val; + + if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) + return (0xffff); + return (le16toh(val)); +} + +static __inline uint32_t +urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) +{ + uint32_t val; + + if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) + return (0xffffffff); + return (le32toh(val)); +} + +static int +urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) +{ + uint8_t hmebox[4]; + uint8_t hmeboxext[2]; + int fwcur; + int ntries; + + DPRINTFN(DBG_FN, ("%s: %s: id=%d, buf=%p, len=%d\n", + device_xname(sc->sc_dev), __func__, id, buf, len)); + + KASSERT(len >= 1 && len <= 5); + + mutex_enter(&sc->sc_fwcmd_mtx); + fwcur = sc->fwcur; + sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; + mutex_exit(&sc->sc_fwcmd_mtx); + + /* Wait for current FW box to be empty. */ + for (ntries = 0; ntries < 100; ntries++) { + if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) + break; + DELAY(10); + } + if (ntries == 100) { + aprint_error_dev(sc->sc_dev, + "could not send firmware command %d\n", id); + return (ETIMEDOUT); + } + + /* Write the first word last since that will trigger the FW. */ + memset(hmebox, 0, sizeof(hmebox)); + hmebox[0] = id; + if (len >= 4) { + hmebox[0] |= R92C_CMD_FLAG_EXT; + memcpy(hmeboxext, buf, 2); + memcpy(&hmebox[1], (const uint8_t *)buf + 2, len - 2); + urtwn_write_region_1(sc, R92C_HMEBOX_EXT(fwcur), hmeboxext, 2); + } else { + hmebox[0] &= ~R92C_CMD_FLAG_EXT; + memcpy(&hmebox[1], buf, len); + } + urtwn_write_region_1(sc, R92C_HMEBOX(fwcur), hmebox, 4); + + return (0); +} + +static __inline void +urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) +{ + + urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), + SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); +} + +static uint32_t +urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) +{ + uint32_t reg[R92C_MAX_CHAINS], val; + + reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); + if (chain != 0) + reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); + + urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), + reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); + DELAY(1000); + + urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), + RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | + R92C_HSSI_PARAM2_READ_EDGE); + DELAY(1000); + + urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), + reg[0] | R92C_HSSI_PARAM2_READ_EDGE); + DELAY(1000); + + if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) + val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); + else + val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); + return (MS(val, R92C_LSSI_READBACK_DATA)); +} + +static int +urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) +{ + int ntries; + + urtwn_write_4(sc, R92C_LLT_INIT, + SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | + SM(R92C_LLT_INIT_ADDR, addr) | + SM(R92C_LLT_INIT_DATA, data)); + /* Wait for write operation to complete. */ + for (ntries = 0; ntries < 20; ntries++) { + if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == + R92C_LLT_INIT_OP_NO_ACTIVE) + return (0); + DELAY(5); + } + return (ETIMEDOUT); +} + +static uint8_t +urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) +{ + uint32_t reg; + int ntries; + + reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); + reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); + reg &= ~R92C_EFUSE_CTRL_VALID; + urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); + /* Wait for read operation to complete. */ + for (ntries = 0; ntries < 100; ntries++) { + reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); + if (reg & R92C_EFUSE_CTRL_VALID) + return (MS(reg, R92C_EFUSE_CTRL_DATA)); + DELAY(5); + } + aprint_error_dev(sc->sc_dev, + "could not read efuse byte at address 0x%04x\n", addr); + return (0xff); +} + +static void +urtwn_efuse_read(struct urtwn_softc *sc) +{ + uint8_t *rom = (uint8_t *)&sc->rom; + uint16_t addr = 0; + uint32_t reg; + uint8_t off, msk; + int i; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); + if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { + urtwn_write_2(sc, R92C_SYS_ISO_CTRL, + reg | R92C_SYS_ISO_CTRL_PWC_EV12V); + } + reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); + if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { + urtwn_write_2(sc, R92C_SYS_FUNC_EN, + reg | R92C_SYS_FUNC_EN_ELDR); + } + reg = urtwn_read_2(sc, R92C_SYS_CLKR); + if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != + (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { + urtwn_write_2(sc, R92C_SYS_CLKR, + reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); + } + memset(&sc->rom, 0xff, sizeof(sc->rom)); + while (addr < 512) { + reg = urtwn_efuse_read_1(sc, addr); + if (reg == 0xff) + break; + addr++; + off = reg >> 4; + msk = reg & 0xf; + for (i = 0; i < 4; i++) { + if (msk & (1 << i)) + continue; + rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); + addr++; + rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); + addr++; + } + } +#ifdef URTWN_DEBUG + if (urtwn_debug & DBG_INIT) { + /* Dump ROM content. */ + printf("%s: %s", device_xname(sc->sc_dev), __func__); + for (i = 0; i < sizeof(sc->rom); i++) + printf(":%02x", rom[i]); + printf("\n"); + } +#endif +} + +static int +urtwn_read_chipid(struct urtwn_softc *sc) +{ + uint32_t reg; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + reg = urtwn_read_4(sc, R92C_SYS_CFG); + if (reg & R92C_SYS_CFG_TRP_VAUX_EN) + return (EIO); + + if (reg & R92C_SYS_CFG_TYPE_92C) { + sc->chip |= URTWN_CHIP_92C; + /* Check if it is a castrated 8192C. */ + if (MS(urtwn_read_4(sc, R92C_HPON_FSM), + R92C_HPON_FSM_CHIP_BONDING_ID) == + R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) + sc->chip |= URTWN_CHIP_92C_1T2R; + } + if (reg & R92C_SYS_CFG_VENDOR_UMC) { + sc->chip |= URTWN_CHIP_UMC; + if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) + sc->chip |= URTWN_CHIP_UMC_A_CUT; + } + return (0); +} + +#ifdef URTWN_DEBUG +static void +urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) +{ + + aprint_normal_dev(sc->sc_dev, + "id 0x%04x, dbg_sel 0x%x, vid 0x%x, pid 0x%x\n", + rp->id, rp->dbg_sel, rp->vid, rp->pid); + + aprint_normal_dev(sc->sc_dev, + "usb_opt 0x%x, ep_setting 0x%x, usb_phy 0x%x\n", + rp->usb_opt, rp->ep_setting, rp->usb_phy); + + aprint_normal_dev(sc->sc_dev, + "macaddr %02x:%02x:%02x:%02x:%02x:%02x\n", + rp->macaddr[0], rp->macaddr[1], + rp->macaddr[2], rp->macaddr[3], + rp->macaddr[4], rp->macaddr[5]); + + aprint_normal_dev(sc->sc_dev, + "string %s, subcustomer_id 0x%x\n", + rp->string, rp->subcustomer_id); + + aprint_normal_dev(sc->sc_dev, + "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", + rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], + rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); + + aprint_normal_dev(sc->sc_dev, + "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", + rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], + rp->ht40_1s_tx_pwr[0][2], + rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], + rp->ht40_1s_tx_pwr[1][2]); + + aprint_normal_dev(sc->sc_dev, + "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", + rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, + rp->ht40_2s_tx_pwr_diff[2] & 0xf, + rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, + rp->ht40_2s_tx_pwr_diff[2] >> 4); + + aprint_normal_dev(sc->sc_dev, + "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", + rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, + rp->ht20_tx_pwr_diff[2] & 0xf, + rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, + rp->ht20_tx_pwr_diff[2] >> 4); + + aprint_normal_dev(sc->sc_dev, + "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", + rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, + rp->ofdm_tx_pwr_diff[2] & 0xf, + rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, + rp->ofdm_tx_pwr_diff[2] >> 4); + + aprint_normal_dev(sc->sc_dev, + "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", + rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, + rp->ht40_max_pwr[2] & 0xf, + rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, + rp->ht40_max_pwr[2] >> 4); + + aprint_normal_dev(sc->sc_dev, + "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", + rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, + rp->ht20_max_pwr[2] & 0xf, + rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, + rp->ht20_max_pwr[2] >> 4); + + aprint_normal_dev(sc->sc_dev, + "xtal_calib %d, tssi %d %d, thermal %d\n", + rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); + + aprint_normal_dev(sc->sc_dev, + "rf_opt1 0x%x, rf_opt2 0x%x, rf_opt3 0x%x, rf_opt4 0x%x\n", + rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); + + aprint_normal_dev(sc->sc_dev, + "channnel_plan %d, version %d customer_id 0x%x\n", + rp->channel_plan, rp->version, rp->curstomer_id); +} +#endif + +static void +urtwn_read_rom(struct urtwn_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct r92c_rom *rom = &sc->rom; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Read full ROM image. */ + urtwn_efuse_read(sc); +#ifdef URTWN_DEBUG + if (urtwn_debug & DBG_INIT) + urtwn_dump_rom(sc, rom); +#endif + + /* XXX Weird but this is what the vendor driver does. */ + sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); + sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); + sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); + + DPRINTFN(DBG_INIT, + ("%s: %s: PA setting=0x%x, board=0x%x, regulatory=%d\n", + device_xname(sc->sc_dev), __func__, sc->pa_setting, + sc->board_type, sc->regulatory)); + + IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); +} + +static int +urtwn_media_change(struct ifnet *ifp) +{ +#ifdef URTWN_DEBUG + struct urtwn_softc *sc = ifp->if_softc; +#endif + int error; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + if ((error = ieee80211_media_change(ifp)) != ENETRESET) + return (error); + + if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == + (IFF_UP | IFF_RUNNING)) { + urtwn_stop(ifp, 0); + urtwn_init(ifp); + } + return (0); +} + +/* + * Initialize rate adaptation in firmware. + */ +static int +urtwn_ra_init(struct urtwn_softc *sc) +{ + static const uint8_t map[] = { + 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 + }; + struct ieee80211com *ic = &sc->sc_ic; + struct ieee80211_node *ni = ic->ic_bss; + struct ieee80211_rateset *rs = &ni->ni_rates; + struct r92c_fw_cmd_macid_cfg cmd; + uint32_t rates, basicrates; + uint8_t mode; + int maxrate, maxbasicrate, error, i, j; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Get normal and basic rates mask. */ + rates = basicrates = 0; + maxrate = maxbasicrate = 0; + for (i = 0; i < rs->rs_nrates; i++) { + /* Convert 802.11 rate to HW rate index. */ + for (j = 0; j < __arraycount(map); j++) + if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) + break; + if (j == __arraycount(map)) /* Unknown rate, skip. */ + continue; + rates |= 1U << j; + if (j > maxrate) + maxrate = j; + if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { + basicrates |= 1U << j; + if (j > maxbasicrate) + maxbasicrate = j; + } + } + if (ic->ic_curmode == IEEE80211_MODE_11B) + mode = R92C_RAID_11B; + else + mode = R92C_RAID_11BG; + DPRINTFN(DBG_INIT, ("%s: %s: mode=0x%x rates=0x%x, basicrates=0x%x\n", + device_xname(sc->sc_dev), __func__, mode, rates, basicrates)); + if (basicrates == 0) + basicrates |= 1; /* add 1Mbps */ + + /* Set rates mask for group addressed frames. */ + cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; + cmd.mask = htole32((mode << 28) | basicrates); + error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); + if (error != 0) { + aprint_error_dev(sc->sc_dev, + "could not add broadcast station\n"); + return (error); + } + /* Set initial MRR rate. */ + DPRINTFN(DBG_INIT, ("%s: %s: maxbasicrate=%d\n", + device_xname(sc->sc_dev), __func__, maxbasicrate)); + urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), maxbasicrate); + + /* Set rates mask for unicast frames. */ + cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; + cmd.mask = htole32((mode << 28) | rates); + error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); + if (error != 0) { + aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); + return (error); + } + /* Set initial MRR rate. */ + DPRINTFN(DBG_INIT, ("%s: %s: maxrate=%d\n", device_xname(sc->sc_dev), + __func__, maxrate)); + urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), maxrate); + + /* Indicate highest supported rate. */ + ni->ni_txrate = rs->rs_nrates - 1; + return (0); +} + +static void +urtwn_tsf_sync_enable(struct urtwn_softc *sc) +{ + struct ieee80211_node *ni = sc->sc_ic.ic_bss; + uint64_t tsf; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Enable TSF synchronization. */ + urtwn_write_1(sc, R92C_BCN_CTRL, + urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); + + /* Correct TSF */ + urtwn_write_1(sc, R92C_BCN_CTRL, + urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); + + /* Set initial TSF. */ + tsf = ni->ni_tstamp.tsf; + tsf = le64toh(tsf); + tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); + tsf -= IEEE80211_DUR_TU; + tsf = htole64(tsf); + urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); + urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); + + urtwn_write_1(sc, R92C_BCN_CTRL, + urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); +} + +static void +urtwn_set_led(struct urtwn_softc *sc, int led, int on) +{ + uint8_t reg; + + DPRINTFN(DBG_FN, ("%s: %s: led=%d, on=%d\n", device_xname(sc->sc_dev), + __func__, led, on)); + + if (led == URTWN_LED_LINK) { + reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; + if (!on) + reg |= R92C_LEDCFG0_DIS; + urtwn_write_1(sc, R92C_LEDCFG0, reg); + sc->ledlink = on; /* Save LED state. */ + } +} + +static void +urtwn_calib_to(void *arg) +{ + struct urtwn_softc *sc = arg; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + if (sc->sc_dying) + return; + + /* Do it in a process context. */ + urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); +} + +/* ARGSUSED */ +static void +urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) +{ + struct r92c_fw_cmd_rssi cmd; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + if (sc->avg_pwdb != -1) { + /* Indicate Rx signal strength to FW for rate adaptation. */ + memset(&cmd, 0, sizeof(cmd)); + cmd.macid = 0; /* BSS. */ + cmd.pwdb = sc->avg_pwdb; + DPRINTFN(DBG_RF, ("%s: %s: sending RSSI command avg=%d\n", + device_xname(sc->sc_dev), __func__, sc->avg_pwdb)); + urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); + } + + /* Do temperature compensation. */ + urtwn_temp_calib(sc); + + if (!sc->sc_dying) { + /* Restart calibration timer. */ + callout_schedule(&sc->sc_calib_to, hz); + } +} + +static void +urtwn_next_scan(void *arg) +{ + struct urtwn_softc *sc = arg; + int s; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + if (sc->sc_dying) + return; + + s = splnet(); + if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) + ieee80211_next_scan(&sc->sc_ic); + splx(s); +} + +static int +urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) +{ + struct urtwn_softc *sc = ic->ic_ifp->if_softc; + struct urtwn_cmd_newstate cmd; + + DPRINTFN(DBG_FN, ("%s: %s: nstate=%s(%d), arg=%d\n", + device_xname(sc->sc_dev), __func__, + ieee80211_state_name[nstate], nstate, arg)); + + /* Do it in a process context. */ + cmd.state = nstate; + cmd.arg = arg; + urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); + return (0); +} + +static void +urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) +{ + struct urtwn_cmd_newstate *cmd = arg; + struct ieee80211com *ic = &sc->sc_ic; + struct ieee80211_node *ni; + enum ieee80211_state ostate = ic->ic_state; + enum ieee80211_state nstate = cmd->state; + uint32_t reg; + uint8_t sifs_time; + int s; + + DPRINTFN(DBG_FN|DBG_STM, ("%s: %s: %s(%d)->%s(%d)\n", + device_xname(sc->sc_dev), __func__, + ieee80211_state_name[ostate], ostate, + ieee80211_state_name[nstate], nstate)); + + s = splnet(); + switch (ostate) { + case IEEE80211_S_INIT: + break; + + case IEEE80211_S_SCAN: + if (nstate != IEEE80211_S_SCAN) { + /* + * End of scanning + */ + /* flush 4-AC Queue after site_survey */ + urtwn_write_1(sc, R92C_TXPAUSE, 0x0); + + /* Allow Rx from our BSSID only. */ + urtwn_write_4(sc, R92C_RCR, + urtwn_read_4(sc, R92C_RCR) | + R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); + } + break; + + case IEEE80211_S_AUTH: + case IEEE80211_S_ASSOC: + break; + + case IEEE80211_S_RUN: + /* Stop calibration. */ + callout_halt(&sc->sc_calib_to, NULL); + + /* Turn link LED off. */ + urtwn_set_led(sc, URTWN_LED_LINK, 0); + + /* Set media status to 'No Link'. */ + reg = urtwn_read_4(sc, R92C_CR); + reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); + urtwn_write_4(sc, R92C_CR, reg); + + /* Stop Rx of data frames. */ + urtwn_write_2(sc, R92C_RXFLTMAP2, 0); + + /* Rest TSF. */ + urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); + + /* Disable TSF synchronization. */ + urtwn_write_1(sc, R92C_BCN_CTRL, + urtwn_read_1(sc, R92C_BCN_CTRL) | + R92C_BCN_CTRL_DIS_TSF_UDT0); + + /* Reset EDCA parameters. */ + urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); + urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); + urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); + urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); + + /* flush all cam entries */ + urtwn_cam_init(sc); + break; + } + + switch (nstate) { + case IEEE80211_S_INIT: + /* Turn link LED off. */ + urtwn_set_led(sc, URTWN_LED_LINK, 0); + break; + + case IEEE80211_S_SCAN: + if (ostate != IEEE80211_S_SCAN) { + /* + * Begin of scanning + */ + /* Allow Rx from any BSSID. */ + urtwn_write_4(sc, R92C_RCR, + urtwn_read_4(sc, R92C_RCR) & + ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); + + /* Set gain for scanning. */ + reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); + reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); + urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); + + reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); + reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); + urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); + + reg = urtwn_read_4(sc, R92C_CR); + reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); + urtwn_write_4(sc, R92C_CR, reg); + + /* Stop Rx of data frames. */ + urtwn_write_2(sc, R92C_RXFLTMAP2, 0); + + /* Disable update TSF */ + urtwn_write_1(sc, R92C_BCN_CTRL, + urtwn_read_1(sc, R92C_BCN_CTRL) | + R92C_BCN_CTRL_DIS_TSF_UDT0); + } + + /* Make link LED blink during scan. */ + urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); + + /* Pause AC Tx queues. */ + urtwn_write_1(sc, R92C_TXPAUSE, + urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); + + urtwn_set_chan(sc, ic->ic_bss->ni_chan, + IEEE80211_HTINFO_2NDCHAN_NONE); + + /* Start periodic scan. */ + if (!sc->sc_dying) + callout_schedule(&sc->sc_scan_to, hz / 5); + break; + + case IEEE80211_S_AUTH: + /* Set initial gain under link. */ + reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); + reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); + urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); + + reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); + reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); + urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); + + reg = urtwn_read_4(sc, R92C_CR); + reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); + urtwn_write_4(sc, R92C_CR, reg); + + /* Allow Rx from any BSSID. */ + urtwn_write_4(sc, R92C_RCR, + urtwn_read_4(sc, R92C_RCR) & + ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); + + urtwn_set_chan(sc, ic->ic_bss->ni_chan, + IEEE80211_HTINFO_2NDCHAN_NONE); + break; + + case IEEE80211_S_ASSOC: + break; + + case IEEE80211_S_RUN: + ni = ic->ic_bss; + ieee80211_fix_rate(ni, IEEE80211_F_DOSORT); + + if (ic->ic_opmode == IEEE80211_M_MONITOR) { + urtwn_set_chan(sc, ic->ic_ibss_chan, + IEEE80211_HTINFO_2NDCHAN_NONE); + + /* Enable Rx of data frames. */ + urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); + + /* Turn link LED on. */ + urtwn_set_led(sc, URTWN_LED_LINK, 1); + break; + } + + /* Set media status to 'Associated'. */ + reg = urtwn_read_4(sc, R92C_CR); + reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); + urtwn_write_4(sc, R92C_CR, reg); + + /* Set BSSID. */ + urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); + urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); + + if (ic->ic_curmode == IEEE80211_MODE_11B) + urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); + else /* 802.11b/g */ + urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); + + /* Enable Rx of data frames. */ + urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); + + /* Flush all AC queues. */ + urtwn_write_1(sc, R92C_TXPAUSE, 0); + + /* Set beacon interval. */ + urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); + + /* Allow Rx from our BSSID only. */ + urtwn_write_4(sc, R92C_RCR, + urtwn_read_4(sc, R92C_RCR) | + R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); + + /* Enable TSF synchronization. */ + urtwn_tsf_sync_enable(sc); + + sifs_time = 10; + urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); + urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); + urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); + urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); + urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); + urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); + + /* Intialize rate adaptation. */ + urtwn_ra_init(sc); + + /* Turn link LED on. */ + urtwn_set_led(sc, URTWN_LED_LINK, 1); + + /* Reset average RSSI. */ + sc->avg_pwdb = -1; + + /* Reset temperature calibration state machine. */ + sc->thcal_state = 0; + sc->thcal_lctemp = 0; + + /* Start periodic calibration. */ + if (!sc->sc_dying) + callout_schedule(&sc->sc_calib_to, hz); + break; + } + (void) (*sc->sc_newstate)(ic, nstate, cmd->arg); + splx(s); +} + +static int +urtwn_wme_update(struct ieee80211com *ic) +{ + struct urtwn_softc *sc = ic->ic_ifp->if_softc; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* don't override default WME values if WME is not actually enabled */ + if (!(ic->ic_flags & IEEE80211_F_WME)) + return (0); + + /* Do it in a process context. */ + urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); + return (0); +} + +static void +urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) +{ + static const uint16_t ac2reg[WME_NUM_AC] = { + R92C_EDCA_BE_PARAM, + R92C_EDCA_BK_PARAM, + R92C_EDCA_VI_PARAM, + R92C_EDCA_VO_PARAM + }; + struct ieee80211com *ic = &sc->sc_ic; + const struct wmeParams *wmep; + int ac, aifs, slottime; + int s; + + DPRINTFN(DBG_FN|DBG_STM, ("%s: %s\n", device_xname(sc->sc_dev), + __func__)); + + s = splnet(); + slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; + for (ac = 0; ac < WME_NUM_AC; ac++) { + wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; + /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ + aifs = wmep->wmep_aifsn * slottime + 10; + urtwn_write_4(sc, ac2reg[ac], + SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | + SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | + SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | + SM(R92C_EDCA_PARAM_AIFS, aifs)); + } + splx(s); +} + +static void +urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) +{ + int pwdb; + + DPRINTFN(DBG_FN, ("%s: %s: rate=%d, rsst=%d\n", + device_xname(sc->sc_dev), __func__, rate, rssi)); + + /* Convert antenna signal to percentage. */ + if (rssi <= -100 || rssi >= 20) + pwdb = 0; + else if (rssi >= 0) + pwdb = 100; + else + pwdb = 100 + rssi; + if (rate <= 3) { + /* CCK gain is smaller than OFDM/MCS gain. */ + pwdb += 6; + if (pwdb > 100) + pwdb = 100; + if (pwdb <= 14) + pwdb -= 4; + else if (pwdb <= 26) + pwdb -= 8; + else if (pwdb <= 34) + pwdb -= 6; + else if (pwdb <= 42) + pwdb -= 2; + } + if (sc->avg_pwdb == -1) /* Init. */ + sc->avg_pwdb = pwdb; + else if (sc->avg_pwdb < pwdb) + sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; + else + sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); + + DPRINTFN(DBG_RF, ("%s: %s: PWDB=%d EMA=%d\n", device_xname(sc->sc_dev), + __func__, pwdb, sc->avg_pwdb)); +} + +static int8_t +urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) +{ + static const int8_t cckoff[] = { 16, -12, -26, -46 }; + struct r92c_rx_phystat *phy; + struct r92c_rx_cck *cck; + uint8_t rpt; + int8_t rssi; + + DPRINTFN(DBG_FN, ("%s: %s: rate=%d\n", device_xname(sc->sc_dev), + __func__, rate)); + + if (rate <= 3) { + cck = (struct r92c_rx_cck *)physt; + if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { + rpt = (cck->agc_rpt >> 5) & 0x3; + rssi = (cck->agc_rpt & 0x1f) << 1; + } else { + rpt = (cck->agc_rpt >> 6) & 0x3; + rssi = cck->agc_rpt & 0x3e; + } + rssi = cckoff[rpt] - rssi; + } else { /* OFDM/HT. */ + phy = (struct r92c_rx_phystat *)physt; + rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; + } + return (rssi); +} + +static void +urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct ieee80211_frame *wh; + struct ieee80211_node *ni; + struct r92c_rx_stat *stat; + uint32_t rxdw0, rxdw3; + struct mbuf *m; + uint8_t rate; + int8_t rssi = 0; + int s, infosz; + + DPRINTFN(DBG_FN, ("%s: %s: buf=%p, pktlen=%d\n", + device_xname(sc->sc_dev), __func__, buf, pktlen)); + + stat = (struct r92c_rx_stat *)buf; + rxdw0 = le32toh(stat->rxdw0); + rxdw3 = le32toh(stat->rxdw3); + + if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { + /* + * This should not happen since we setup our Rx filter + * to not receive these frames. + */ + DPRINTFN(DBG_RX, ("%s: %s: CRC error\n", + device_xname(sc->sc_dev), __func__)); + ifp->if_ierrors++; + return; + } + if (__predict_false(pktlen < sizeof(*wh))) { + DPRINTFN(DBG_RX, ("%s: %s: packet too short %d\n", + device_xname(sc->sc_dev), __func__, pktlen)); + ic->ic_stats.is_rx_tooshort++; + ifp->if_ierrors++; + return; + } + if (__predict_false(pktlen > MCLBYTES)) { + DPRINTFN(DBG_RX, ("%s: %s: packet too big %d\n", + device_xname(sc->sc_dev), __func__, pktlen)); + ifp->if_ierrors++; + return; + } + + rate = MS(rxdw3, R92C_RXDW3_RATE); + infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; + + /* Get RSSI from PHY status descriptor if present. */ + if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { + rssi = urtwn_get_rssi(sc, rate, &stat[1]); + /* Update our average RSSI. */ + urtwn_update_avgrssi(sc, rate, rssi); + } + + DPRINTFN(DBG_RX, ("%s: %s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", + device_xname(sc->sc_dev), __func__, pktlen, rate, infosz, rssi)); + + MGETHDR(m, M_DONTWAIT, MT_DATA); + if (__predict_false(m == NULL)) { + aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); + ic->ic_stats.is_rx_nobuf++; + ifp->if_ierrors++; + return; + } + if (pktlen > MHLEN) { + MCLGET(m, M_DONTWAIT); + if (__predict_false(!(m->m_flags & M_EXT))) { + aprint_error_dev(sc->sc_dev, + "couldn't allocate rx mbuf cluster\n"); + m_freem(m); + ic->ic_stats.is_rx_nobuf++; + ifp->if_ierrors++; + return; + } + } + + /* Finalize mbuf. */ + m->m_pkthdr.rcvif = ifp; + wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); + memcpy(mtod(m, uint8_t *), wh, pktlen); + m->m_pkthdr.len = m->m_len = pktlen; + + s = splnet(); + if (__predict_false(sc->sc_drvbpf != NULL)) { + struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; + + tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; + if (!(rxdw3 & R92C_RXDW3_HT)) { + switch (rate) { + /* CCK. */ + case 0: tap->wr_rate = 2; break; + case 1: tap->wr_rate = 4; break; + case 2: tap->wr_rate = 11; break; + case 3: tap->wr_rate = 22; break; + /* OFDM. */ + case 4: tap->wr_rate = 12; break; + case 5: tap->wr_rate = 18; break; + case 6: tap->wr_rate = 24; break; + case 7: tap->wr_rate = 36; break; + case 8: tap->wr_rate = 48; break; + case 9: tap->wr_rate = 72; break; + case 10: tap->wr_rate = 96; break; + case 11: tap->wr_rate = 108; break; + } + } else if (rate >= 12) { /* MCS0~15. */ + /* Bit 7 set means HT MCS instead of rate. */ + tap->wr_rate = 0x80 | (rate - 12); + } + tap->wr_dbm_antsignal = rssi; + tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); + tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); + + bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); + } + + ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); + + /* push the frame up to the 802.11 stack */ + ieee80211_input(ic, m, ni, rssi, 0); + + /* Node is no longer needed. */ + ieee80211_free_node(ni); + + splx(s); +} + +static void +urtwn_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) +{ + struct urtwn_rx_data *data = priv; + struct urtwn_softc *sc = data->sc; + struct r92c_rx_stat *stat; + uint32_t rxdw0; + uint8_t *buf; + int len, totlen, pktlen, infosz, npkts; + + DPRINTFN(DBG_FN|DBG_RX, ("%s: %s: status=%d\n", + device_xname(sc->sc_dev), __func__, status)); + + if (__predict_false(status != USBD_NORMAL_COMPLETION)) { + if (status == USBD_STALLED) + usbd_clear_endpoint_stall_async(sc->rx_pipe); + else if (status != USBD_CANCELLED) + goto resubmit; + return; + } + usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); + + if (__predict_false(len < sizeof(*stat))) { + DPRINTFN(DBG_RX, ("%s: %s: xfer too short %d\n", + device_xname(sc->sc_dev), __func__, len)); + goto resubmit; + } + buf = data->buf; + + /* Get the number of encapsulated frames. */ + stat = (struct r92c_rx_stat *)buf; + npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); + DPRINTFN(DBG_RX, ("%s: %s: Rx %d frames in one chunk\n", + device_xname(sc->sc_dev), __func__, npkts)); + + /* Process all of them. */ + while (npkts-- > 0) { + if (__predict_false(len < sizeof(*stat))) { + DPRINTFN(DBG_RX, + ("%s: %s: len(%d) is short than header\n", + device_xname(sc->sc_dev), __func__, len)); + break; + } + stat = (struct r92c_rx_stat *)buf; + rxdw0 = le32toh(stat->rxdw0); + + pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); + if (__predict_false(pktlen == 0)) { + DPRINTFN(DBG_RX, ("%s: %s: pktlen is 0 byte\n", + device_xname(sc->sc_dev), __func__)); + break; + } + + infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; + + /* Make sure everything fits in xfer. */ + totlen = sizeof(*stat) + infosz + pktlen; + if (__predict_false(totlen > len)) { + DPRINTFN(DBG_RX, ("%s: %s: pktlen %d(%d+%d+%d) > %d\n", + device_xname(sc->sc_dev), __func__, totlen, + (int)sizeof(*stat), infosz, pktlen, len)); + break; + } + + /* Process 802.11 frame. */ + urtwn_rx_frame(sc, buf, pktlen); + + /* Next chunk is 128-byte aligned. */ + totlen = roundup2(totlen, 128); + buf += totlen; + len -= totlen; + } + + resubmit: + /* Setup a new transfer. */ + usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, + USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); + (void)usbd_transfer(xfer); +} + +static void +urtwn_txeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) +{ + struct urtwn_tx_data *data = priv; + struct urtwn_softc *sc = data->sc; + struct ifnet *ifp = &sc->sc_if; + int s; + + DPRINTFN(DBG_FN|DBG_TX, ("%s: %s: status=%d\n", + device_xname(sc->sc_dev), __func__, status)); + + mutex_enter(&sc->sc_tx_mtx); + /* Put this Tx buffer back to our free list. */ + TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); + mutex_exit(&sc->sc_tx_mtx); + + if (__predict_false(status != USBD_NORMAL_COMPLETION)) { + if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { + if (status == USBD_STALLED) + usbd_clear_endpoint_stall_async(data->pipe); + ifp->if_oerrors++; + } + return; + } + + ifp->if_opackets++; + + s = splnet(); + sc->tx_timer = 0; + ifp->if_flags &= ~IFF_OACTIVE; + splx(s); + + urtwn_start(ifp); +} + +static int +urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ieee80211_frame *wh; + struct ieee80211_key *k = NULL; + struct urtwn_tx_data *data; + struct r92c_tx_desc *txd; + usbd_pipe_handle pipe; + uint16_t seq, sum; + uint8_t raid, type, tid, qid; + int i, s, hasqos, xferlen, padsize, error; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + wh = mtod(m, struct ieee80211_frame *); + type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; + + if (wh->i_fc[1] & IEEE80211_FC1_WEP) { + k = ieee80211_crypto_encap(ic, ni, m); + if (k == NULL) { + m_freem(m); + return (ENOBUFS); + } + /* packet header may have moved, reset our local pointer */ + wh = mtod(m, struct ieee80211_frame *); + } + + if (__predict_false(sc->sc_drvbpf != NULL)) { + struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); + tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); + if (wh->i_fc[1] & IEEE80211_FC1_WEP) + tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; + + bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); + } + + if ((hasqos = IEEE80211_QOS_HAS_SEQ(wh))) { + /* data frames in 11n mode */ + struct ieee80211_qosframe *qwh = (void *)wh; + tid = qwh->i_qos[0] & IEEE80211_QOS_TID; + qid = TID_TO_WME_AC(tid); + } else if (type != IEEE80211_FC0_TYPE_DATA) { + /* Use AC_VO for management frames. */ + qid = WME_AC_VO; + tid = 0; /* compiler happy */ + } else { + /* non-qos data frames */ + tid = R92C_TXDW1_QSEL_BE; + qid = WME_AC_BE; + } + + /* Get the USB pipe to use for this AC. */ + pipe = sc->tx_pipe[sc->ac2idx[qid]]; + + /* Grab a Tx buffer from our free list. */ + mutex_enter(&sc->sc_tx_mtx); + data = TAILQ_FIRST(&sc->tx_free_list); + TAILQ_REMOVE(&sc->tx_free_list, data, next); + mutex_exit(&sc->sc_tx_mtx); + + if (((sizeof(*txd) + m->m_pkthdr.len) % 64) == 0) + padsize = 8; + else + padsize = 0; + + /* Fill Tx descriptor. */ + txd = (struct r92c_tx_desc *)data->buf; + memset(txd, 0, sizeof(*txd) + padsize); + + txd->txdw0 |= htole32( + SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | + SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | + R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); + + if (IEEE80211_IS_MULTICAST(wh->i_addr1)) + txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); + + /* fix pad field */ + if (padsize > 0) { + DPRINTFN(DBG_TX, ("%s: %s: padding: size=%d\n", + device_xname(sc->sc_dev), __func__, padsize)); + txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); + } + + if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && + type == IEEE80211_FC0_TYPE_DATA) { + if (ic->ic_curmode == IEEE80211_MODE_11B) + raid = R92C_RAID_11B; + else + raid = R92C_RAID_11BG; + DPRINTFN(DBG_TX, + ("%s: %s: data packet: tid=%d, raid=%d\n", + device_xname(sc->sc_dev), __func__, tid, raid)); + + txd->txdw1 |= htole32( + SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | + SM(R92C_TXDW1_QSEL, tid) | + SM(R92C_TXDW1_RAID, raid) | + R92C_TXDW1_AGGBK); + + if (hasqos) + txd->txdw4 |= htole32(R92C_TXDW4_QOS); + + if (ic->ic_flags & IEEE80211_F_USEPROT) { + if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { + txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | + R92C_TXDW4_HWRTSEN); + } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { + txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | + R92C_TXDW4_HWRTSEN); + } + } + /* Send RTS at OFDM24. */ + txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); + txd->txdw5 |= htole32(0x0001ff00); + /* Send data at OFDM54. */ + txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); + } else if (type == IEEE80211_FC0_TYPE_MGT) { + DPRINTFN(DBG_TX, ("%s: %s: mgmt packet\n", + device_xname(sc->sc_dev), __func__)); + txd->txdw1 |= htole32( + SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | + SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | + SM(R92C_TXDW1_RAID, R92C_RAID_11B)); + + /* Force CCK1. */ + txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); + /* Use 1Mbps */ + txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); + } else { + /* broadcast or multicast packets */ + DPRINTFN(DBG_TX, ("%s: %s: bc or mc packet\n", + device_xname(sc->sc_dev), __func__)); + txd->txdw1 |= htole32( + SM(R92C_TXDW1_MACID, URTWN_MACID_BC) | + SM(R92C_TXDW1_RAID, R92C_RAID_11B)); + + /* Force CCK1. */ + txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); + /* Use 1Mbps */ + txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); + } + + /* Set sequence number */ + seq = ((wh->i_seq[1] << 8) | wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; + txd->txdseq |= htole16(seq); + + if (!hasqos) { + /* Use HW sequence numbering for non-QoS frames. */ + txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); + txd->txdseq |= htole16(0x8000); /* WTF? */ + } + + /* Compute Tx descriptor checksum. */ + sum = 0; + for (i = 0; i < sizeof(*txd) / 2; i++) + sum ^= ((uint16_t *)txd)[i]; + txd->txdsum = sum; /* NB: already little endian. */ + + xferlen = sizeof(*txd) + m->m_pkthdr.len + padsize; + m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[1] + padsize); + m_freem(m); + + s = splnet(); + data->pipe = pipe; + usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, + USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, + urtwn_txeof); + error = usbd_transfer(data->xfer); + if (__predict_false(error != USBD_NORMAL_COMPLETION && + error != USBD_IN_PROGRESS)) { + splx(s); + DPRINTFN(DBG_TX, ("%s: %s: transfer failed %d\n", + device_xname(sc->sc_dev), __func__, error)); + mutex_enter(&sc->sc_tx_mtx); + /* Put this Tx buffer back to our free list. */ + TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); + mutex_exit(&sc->sc_tx_mtx); + return (error); + } + splx(s); + ieee80211_free_node(ni); + return (0); +} + +static void +urtwn_start(struct ifnet *ifp) +{ + struct urtwn_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + struct ether_header *eh; + struct ieee80211_node *ni; + struct mbuf *m; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) + return; + + for (;;) { + mutex_enter(&sc->sc_tx_mtx); + if (TAILQ_EMPTY(&sc->tx_free_list)) { + mutex_exit(&sc->sc_tx_mtx); + ifp->if_flags |= IFF_OACTIVE; + break; + } + mutex_exit(&sc->sc_tx_mtx); + + /* Send pending management frames first. */ + IF_DEQUEUE(&ic->ic_mgtq, m); + if (m != NULL) { + ni = (void *)m->m_pkthdr.rcvif; + m->m_pkthdr.rcvif = NULL; + goto sendit; + } + if (ic->ic_state != IEEE80211_S_RUN) + break; + + /* Encapsulate and send data frames. */ + IFQ_DEQUEUE(&ifp->if_snd, m); + if (m == NULL) + break; + if (m->m_len < sizeof(*eh) && + (m = m_pullup(m, sizeof(*eh))) == NULL) { + ifp->if_oerrors++; + continue; + } + eh = mtod(m, struct ether_header *); + ni = ieee80211_find_txnode(ic, eh->ether_dhost); + if (ni == NULL) { + m_freem(m); + ifp->if_oerrors++; + continue; + } + + bpf_mtap(ifp, m); + + if ((m = ieee80211_encap(ic, m, ni)) == NULL) { + ieee80211_free_node(ni); + ifp->if_oerrors++; + continue; + } + sendit: + bpf_mtap3(ic->ic_rawbpf, m); + + if (urtwn_tx(sc, m, ni) != 0) { + ieee80211_free_node(ni); + ifp->if_oerrors++; + continue; + } + + sc->tx_timer = 5; + ifp->if_timer = 1; + } +} + +static void +urtwn_watchdog(struct ifnet *ifp) +{ + struct urtwn_softc *sc = ifp->if_softc; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + ifp->if_timer = 0; + + if (sc->tx_timer > 0) { + if (--sc->tx_timer == 0) { + aprint_error_dev(sc->sc_dev, "device timeout\n"); + /* urtwn_init(ifp); XXX needs a process context! */ + ifp->if_oerrors++; + return; + } + ifp->if_timer = 1; + } + ieee80211_watchdog(&sc->sc_ic); +} + +static int +urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) +{ + struct urtwn_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + int s, error = 0; + + DPRINTFN(DBG_FN, ("%s: %s: cmd=0x%08lx, data=%p\n", + device_xname(sc->sc_dev), __func__, cmd, data)); + + s = splnet(); + + switch (cmd) { + case SIOCSIFFLAGS: + if ((error = ifioctl_common(ifp, cmd, data)) != 0) + break; + switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { + case IFF_UP|IFF_RUNNING: + break; + case IFF_UP: + urtwn_init(ifp); + break; + case IFF_RUNNING: + urtwn_stop(ifp, 1); + break; + case 0: + break; + } + break; + + case SIOCADDMULTI: + case SIOCDELMULTI: + if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { + /* setup multicast filter, etc */ + error = 0; + } + break; + + case SIOCS80211CHANNEL: + error = ieee80211_ioctl(ic, cmd, data); + if (error == ENETRESET && + ic->ic_opmode == IEEE80211_M_MONITOR) { + if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == + (IFF_UP | IFF_RUNNING)) { + urtwn_set_chan(sc, ic->ic_ibss_chan, + IEEE80211_HTINFO_2NDCHAN_NONE); + } + error = 0; + } + break; + + default: + error = ieee80211_ioctl(ic, cmd, data); + break; + } + if (error == ENETRESET) { + if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == + (IFF_UP | IFF_RUNNING)) { + urtwn_stop(ifp, 0); + urtwn_init(ifp); + } + error = 0; + } + + splx(s); + + return (error); +} + +static int +urtwn_power_on(struct urtwn_softc *sc) +{ + uint32_t reg; + int ntries; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Wait for autoload done bit. */ + for (ntries = 0; ntries < 1000; ntries++) { + if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) + break; + DELAY(5); + } + if (ntries == 1000) { + aprint_error_dev(sc->sc_dev, + "timeout waiting for chip autoload\n"); + return (ETIMEDOUT); + } + + /* Unlock ISO/CLK/Power control register. */ + urtwn_write_1(sc, R92C_RSV_CTRL, 0); + /* Move SPS into PWM mode. */ + urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); + DELAY(100); + + reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); + if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { + urtwn_write_1(sc, R92C_LDOV12D_CTRL, + reg | R92C_LDOV12D_CTRL_LDV12_EN); + DELAY(100); + urtwn_write_1(sc, R92C_SYS_ISO_CTRL, + urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & + ~R92C_SYS_ISO_CTRL_MD2PP); + } + + /* Auto enable WLAN. */ + urtwn_write_2(sc, R92C_APS_FSMCO, + urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); + for (ntries = 0; ntries < 1000; ntries++) { + if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & + R92C_APS_FSMCO_APFM_ONMAC)) + break; + DELAY(5); + } + if (ntries == 1000) { + aprint_error_dev(sc->sc_dev, + "timeout waiting for MAC auto ON\n"); + return (ETIMEDOUT); + } + + /* Enable radio, GPIO and LED functions. */ + urtwn_write_2(sc, R92C_APS_FSMCO, + R92C_APS_FSMCO_AFSM_HSUS | + R92C_APS_FSMCO_PDN_EN | + R92C_APS_FSMCO_PFM_ALDN); + + /* Release RF digital isolation. */ + urtwn_write_2(sc, R92C_SYS_ISO_CTRL, + urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); + + /* Initialize MAC. */ + urtwn_write_1(sc, R92C_APSD_CTRL, + urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); + for (ntries = 0; ntries < 200; ntries++) { + if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & + R92C_APSD_CTRL_OFF_STATUS)) + break; + DELAY(5); + } + if (ntries == 200) { + aprint_error_dev(sc->sc_dev, + "timeout waiting for MAC initialization\n"); + return (ETIMEDOUT); + } + + /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ + reg = urtwn_read_2(sc, R92C_CR); + reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | + R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | + R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | + R92C_CR_ENSEC; + urtwn_write_2(sc, R92C_CR, reg); + + urtwn_write_1(sc, 0xfe10, 0x19); + return (0); +} + +static int +urtwn_llt_init(struct urtwn_softc *sc) +{ + int i, error; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ + for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { + if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) + return (error); + } + /* NB: 0xff indicates end-of-list. */ + if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) + return (error); + /* + * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] + * as ring buffer. + */ + for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { + if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) + return (error); + } + /* Make the last page point to the beginning of the ring buffer. */ + error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); + return (error); +} + +static void +urtwn_fw_reset(struct urtwn_softc *sc) +{ + uint16_t reg; + int ntries; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Tell 8051 to reset itself. */ + urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); + + /* Wait until 8051 resets by itself. */ + for (ntries = 0; ntries < 100; ntries++) { + reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); + if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) + return; + DELAY(50); + } + /* Force 8051 reset. */ + urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); +} + +static int +urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) +{ + uint32_t reg; + int off, mlen, error = 0; + + DPRINTFN(DBG_FN, ("%s: %s: page=%d, buf=%p, len=%d\n", + device_xname(sc->sc_dev), __func__, page, buf, len)); + + reg = urtwn_read_4(sc, R92C_MCUFWDL); + reg = RW(reg, R92C_MCUFWDL_PAGE, page); + urtwn_write_4(sc, R92C_MCUFWDL, reg); + + off = R92C_FW_START_ADDR; + while (len > 0) { + if (len > 196) + mlen = 196; + else if (len > 4) + mlen = 4; + else + mlen = 1; + error = urtwn_write_region_1(sc, off, buf, mlen); + if (error != 0) + break; + off += mlen; + buf += mlen; + len -= mlen; + } + return (error); +} + +static int +urtwn_load_firmware(struct urtwn_softc *sc) +{ + firmware_handle_t fwh; + const struct r92c_fw_hdr *hdr; + const char *name; + u_char *fw, *ptr; + size_t len; + uint32_t reg; + int mlen, ntries, page, error; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Read firmware image from the filesystem. */ + if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == + URTWN_CHIP_UMC_A_CUT) + name = "urtwn-rtl8192cfwU"; + else + name = "urtwn-rtl8192cfwT"; + if ((error = firmware_open("urtwn", name, &fwh)) != 0) { + aprint_error_dev(sc->sc_dev, + "failed loadfirmware of file %s (error %d)\n", name, error); + return (error); + } + len = firmware_get_size(fwh); + fw = firmware_malloc(len); + if (fw == NULL) { + aprint_error_dev(sc->sc_dev, + "failed to allocate firmware memory\n"); + firmware_close(fwh); + return (ENOMEM); + } + error = firmware_read(fwh, 0, fw, len); + firmware_close(fwh); + if (error != 0) { + aprint_error_dev(sc->sc_dev, + "failed to read firmware (error %d)\n", error); + firmware_free(fw, 0); + return (error); + } + + ptr = fw; + hdr = (const struct r92c_fw_hdr *)ptr; + /* Check if there is a valid FW header and skip it. */ + if ((le16toh(hdr->signature) >> 4) == 0x88c || + (le16toh(hdr->signature) >> 4) == 0x92c) { + DPRINTFN(DBG_INIT, ("%s: %s: FW V%d.%d %02d-%02d %02d:%02d\n", + device_xname(sc->sc_dev), __func__, + le16toh(hdr->version), le16toh(hdr->subversion), + hdr->month, hdr->date, hdr->hour, hdr->minute)); + ptr += sizeof(*hdr); + len -= sizeof(*hdr); + } + + if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) { + urtwn_fw_reset(sc); + urtwn_write_1(sc, R92C_MCUFWDL, 0); + } + + /* download enabled */ + urtwn_write_2(sc, R92C_SYS_FUNC_EN, + urtwn_read_2(sc, R92C_SYS_FUNC_EN) | + R92C_SYS_FUNC_EN_CPUEN); + urtwn_write_1(sc, R92C_MCUFWDL, + urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); + urtwn_write_1(sc, R92C_MCUFWDL + 2, + urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); + + /* download firmware */ + for (page = 0; len > 0; page++) { + mlen = MIN(len, R92C_FW_PAGE_SIZE); + error = urtwn_fw_loadpage(sc, page, ptr, mlen); + if (error != 0) { + aprint_error_dev(sc->sc_dev, + "could not load firmware page %d\n", page); + goto fail; + } + ptr += mlen; + len -= mlen; + } + + /* download disable */ + urtwn_write_1(sc, R92C_MCUFWDL, + urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); + urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); + + /* Wait for checksum report. */ + for (ntries = 0; ntries < 1000; ntries++) { + if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) + break; + DELAY(5); + } + if (ntries == 1000) { + aprint_error_dev(sc->sc_dev, + "timeout waiting for checksum report\n"); + error = ETIMEDOUT; + goto fail; + } + + /* Wait for firmware readiness. */ + reg = urtwn_read_4(sc, R92C_MCUFWDL); + reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; + urtwn_write_4(sc, R92C_MCUFWDL, reg); + for (ntries = 0; ntries < 1000; ntries++) { + if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) + break; + DELAY(5); + } + if (ntries == 1000) { + aprint_error_dev(sc->sc_dev, + "timeout waiting for firmware readiness\n"); + error = ETIMEDOUT; + goto fail; + } + fail: + firmware_free(fw, 0); + return (error); +} + +static int +urtwn_dma_init(struct urtwn_softc *sc) +{ + int hashq, hasnq, haslq, nqueues, nqpages, nrempages; + uint32_t reg; + int error; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Initialize LLT table. */ + error = urtwn_llt_init(sc); + if (error != 0) + return (error); + + /* Get Tx queues to USB endpoints mapping. */ + hashq = hasnq = haslq = 0; + reg = urtwn_read_2(sc, R92C_USB_EP + 1); + DPRINTFN(DBG_INIT, ("%s: %s: USB endpoints mapping 0x%x\n", + device_xname(sc->sc_dev), __func__, reg)); + if (MS(reg, R92C_USB_EP_HQ) != 0) + hashq = 1; + if (MS(reg, R92C_USB_EP_NQ) != 0) + hasnq = 1; + if (MS(reg, R92C_USB_EP_LQ) != 0) + haslq = 1; + nqueues = hashq + hasnq + haslq; + if (nqueues == 0) + return (EIO); + /* Get the number of pages for each queue. */ + nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; + /* The remaining pages are assigned to the high priority queue. */ + nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; + + /* Set number of pages for normal priority queue. */ + urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); + urtwn_write_4(sc, R92C_RQPN, + /* Set number of pages for public queue. */ + SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | + /* Set number of pages for high priority queue. */ + SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | + /* Set number of pages for low priority queue. */ + SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | + /* Load values. */ + R92C_RQPN_LD); + + urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); + urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); + urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); + urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); + urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); + + /* Set queue to USB pipe mapping. */ + reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); + reg &= ~R92C_TRXDMA_CTRL_QMAP_M; + if (nqueues == 1) { + if (hashq) + reg |= R92C_TRXDMA_CTRL_QMAP_HQ; + else if (hasnq) + reg |= R92C_TRXDMA_CTRL_QMAP_NQ; + else + reg |= R92C_TRXDMA_CTRL_QMAP_LQ; + } else if (nqueues == 2) { + /* All 2-endpoints configs have a high priority queue. */ + if (!hashq) + return (EIO); + if (hasnq) + reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; + else + reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; + } else + reg |= R92C_TRXDMA_CTRL_QMAP_3EP; + urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); + + /* Set Tx/Rx transfer page boundary. */ + urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); + + /* Set Tx/Rx transfer page size. */ + urtwn_write_1(sc, R92C_PBP, + SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); + return (0); +} + +static void +urtwn_mac_init(struct urtwn_softc *sc) +{ + int i; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Write MAC initialization values. */ + for (i = 0; i < __arraycount(rtl8192cu_mac); i++) + urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val); +} + +static void +urtwn_bb_init(struct urtwn_softc *sc) +{ + const struct urtwn_bb_prog *prog; + uint32_t reg; + int i; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Enable BB and RF. */ + urtwn_write_2(sc, R92C_SYS_FUNC_EN, + urtwn_read_2(sc, R92C_SYS_FUNC_EN) | + R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | + R92C_SYS_FUNC_EN_DIO_RF); + + urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); + + urtwn_write_1(sc, R92C_RF_CTRL, + R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); + urtwn_write_1(sc, R92C_SYS_FUNC_EN, + R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | + R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); + + urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); + urtwn_write_1(sc, 0x15, 0xe9); + urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); + + /* Select BB programming based on board type. */ + if (!(sc->chip & URTWN_CHIP_92C)) { + if (sc->board_type == R92C_BOARD_TYPE_MINICARD) + prog = &rtl8188ce_bb_prog; + else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) + prog = &rtl8188ru_bb_prog; + else + prog = &rtl8188cu_bb_prog; + } else { + if (sc->board_type == R92C_BOARD_TYPE_MINICARD) + prog = &rtl8192ce_bb_prog; + else + prog = &rtl8192cu_bb_prog; + } + /* Write BB initialization values. */ + for (i = 0; i < prog->count; i++) { + /* additional delay depend on registers */ + switch (prog->regs[i]) { + case 0xfe: + usbd_delay_ms(sc->sc_udev, 50); + break; + case 0xfd: + usbd_delay_ms(sc->sc_udev, 5); + break; + case 0xfc: + usbd_delay_ms(sc->sc_udev, 1); + break; + case 0xfb: + DELAY(50); + break; + case 0xfa: + DELAY(5); + break; + case 0xf9: + DELAY(1); + break; + } + urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); + DELAY(1); + } + + if (sc->chip & URTWN_CHIP_92C_1T2R) { + /* 8192C 1T only configuration. */ + reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); + reg = (reg & ~0x00000003) | 0x2; + urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); + + reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); + reg = (reg & ~0x00300033) | 0x00200022; + urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); + + reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); + reg = (reg & ~0xff000000) | (0x45 << 24); + urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); + + reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); + reg = (reg & ~0x000000ff) | 0x23; + urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); + + reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); + reg = (reg & ~0x00000030) | (1 << 4); + urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); + + reg = urtwn_bb_read(sc, 0xe74); + reg = (reg & ~0x0c000000) | (2 << 26); + urtwn_bb_write(sc, 0xe74, reg); + reg = urtwn_bb_read(sc, 0xe78); + reg = (reg & ~0x0c000000) | (2 << 26); + urtwn_bb_write(sc, 0xe78, reg); + reg = urtwn_bb_read(sc, 0xe7c); + reg = (reg & ~0x0c000000) | (2 << 26); + urtwn_bb_write(sc, 0xe7c, reg); + reg = urtwn_bb_read(sc, 0xe80); + reg = (reg & ~0x0c000000) | (2 << 26); + urtwn_bb_write(sc, 0xe80, reg); + reg = urtwn_bb_read(sc, 0xe88); + reg = (reg & ~0x0c000000) | (2 << 26); + urtwn_bb_write(sc, 0xe88, reg); + } + + /* Write AGC values. */ + for (i = 0; i < prog->agccount; i++) { + urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, + prog->agcvals[i]); + DELAY(1); + } + + if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & + R92C_HSSI_PARAM2_CCK_HIPWR) + SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); +} + +static void +urtwn_rf_init(struct urtwn_softc *sc) +{ + const struct urtwn_rf_prog *prog; + uint32_t reg, mask, saved; + int i, j, idx; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Select RF programming based on board type. */ + if (!(sc->chip & URTWN_CHIP_92C)) { + if (sc->board_type == R92C_BOARD_TYPE_MINICARD) + prog = rtl8188ce_rf_prog; + else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) + prog = rtl8188ru_rf_prog; + else + prog = rtl8188cu_rf_prog; + } else + prog = rtl8192ce_rf_prog; + + for (i = 0; i < sc->nrxchains; i++) { + /* Save RF_ENV control type. */ + idx = i / 2; + mask = 0xffffU << ((i % 2) * 16); + saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; + + /* Set RF_ENV enable. */ + reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); + reg |= 0x100000; + urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); + DELAY(1); + + /* Set RF_ENV output high. */ + reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); + reg |= 0x10; + urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); + DELAY(1); + + /* Set address and data lengths of RF registers. */ + reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); + reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; + urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); + DELAY(1); + reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); + reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; + urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); + DELAY(1); + + /* Write RF initialization values for this chain. */ + for (j = 0; j < prog[i].count; j++) { + if (prog[i].regs[j] >= 0xf9 && + prog[i].regs[j] <= 0xfe) { + /* + * These are fake RF registers offsets that + * indicate a delay is required. + */ + usbd_delay_ms(sc->sc_udev, 50); + continue; + } + urtwn_rf_write(sc, i, prog[i].regs[j], + prog[i].vals[j]); + DELAY(1); + } + + /* Restore RF_ENV control type. */ + reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; + urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); + } + + if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == + URTWN_CHIP_UMC_A_CUT) { + urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); + urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); + } + + for (i = 0; i < 2; i++) { + /* Cache RF register CHNLBW. */ + sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); + } +} + +static void +urtwn_cam_init(struct urtwn_softc *sc) +{ + uint32_t content, command; + uint8_t idx; + int i; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { + content = (idx & 3) + | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) + | R92C_CAM_VALID; + + command = R92C_CAMCMD_POLLING + | R92C_CAMCMD_WRITE + | R92C_CAM_CTL0(idx); + + urtwn_write_4(sc, R92C_CAMWRITE, content); + urtwn_write_4(sc, R92C_CAMCMD, command); + } + + for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { + for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { + if (i == 0) { + content = (idx & 3) + | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) + | R92C_CAM_VALID; + } else + content = 0; + + command = R92C_CAMCMD_POLLING + | R92C_CAMCMD_WRITE + | R92C_CAM_CTL0(idx) + | (u_int)i; + + urtwn_write_4(sc, R92C_CAMWRITE, content); + urtwn_write_4(sc, R92C_CAMCMD, command); + } + } + + /* Invalidate all CAM entries. */ + urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); +} + +static void +urtwn_pa_bias_init(struct urtwn_softc *sc) +{ + int i; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + for (i = 0; i < sc->nrxchains; i++) { + if (sc->pa_setting & (1U << i)) + continue; + urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); + urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); + urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); + urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); + } + if (!(sc->pa_setting & 0x10)) { + urtwn_write_1(sc, 0x16, + (urtwn_read_1(sc, 0x16) & 0x0f) | 0x90); + } +} + +static void +urtwn_rxfilter_init(struct urtwn_softc *sc) +{ + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* Initialize Rx filter. */ + /* TODO: use better filter for monitor mode. */ + urtwn_write_4(sc, R92C_RCR, + R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | + R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | + R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); + /* Accept all multicast frames. */ + urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); + urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); + /* Accept all management frames. */ + urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); + /* Reject all control frames. */ + urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); + /* Accept all data frames. */ + urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); +} + +static void +urtwn_edca_init(struct urtwn_softc *sc) +{ + uint32_t reg; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + /* disable EDCA count down */ + reg = urtwn_read_2(sc, R92C_RD_CTRL); + reg |= R92C_RD_CTRL_DIS_EDCA_CNT_DWN; + urtwn_write_2(sc, R92C_RD_CTRL, reg); + + /* set spec SIFS (used in NAV) */ + urtwn_write_2(sc, R92C_SPEC_SIFS, 0x0a0a); + urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x0e0e); + + /* set SIFS CCK/OFDM */ + urtwn_write_2(sc, R92C_SIFS_CCK, 0x0a0a); + urtwn_write_2(sc, R92C_SIFS_OFDM, 0x1010); + urtwn_write_2(sc, R92C_PROT_MODE_CTRL, 0x0204); + urtwn_write_4(sc, R92C_BAR_MODE_CTRL, 0x014004); + + /* TXOP */ + urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); + urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); + urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); + urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); + + /* PIFS */ + urtwn_write_1(sc, R92C_PIFS, 0x1c); +} + +static void +urtwn_write_txpower(struct urtwn_softc *sc, int chain, + uint16_t power[URTWN_RIDX_COUNT]) +{ + uint32_t reg; + + DPRINTFN(DBG_FN, ("%s: %s: chain=%d\n", device_xname(sc->sc_dev), + __func__, chain)); + + /* Write per-CCK rate Tx power. */ + if (chain == 0) { + reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); + reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); + urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); + + reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); + reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); + reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); + reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); + urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); + } else { + reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); + reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); + reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); + reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); + urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); + + reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); + reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); + urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); + } + /* Write per-OFDM rate Tx power. */ + urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), + SM(R92C_TXAGC_RATE06, power[ 4]) | + SM(R92C_TXAGC_RATE09, power[ 5]) | + SM(R92C_TXAGC_RATE12, power[ 6]) | + SM(R92C_TXAGC_RATE18, power[ 7])); + urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), + SM(R92C_TXAGC_RATE24, power[ 8]) | + SM(R92C_TXAGC_RATE36, power[ 9]) | + SM(R92C_TXAGC_RATE48, power[10]) | + SM(R92C_TXAGC_RATE54, power[11])); + /* Write per-MCS Tx power. */ + urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), + SM(R92C_TXAGC_MCS00, power[12]) | + SM(R92C_TXAGC_MCS01, power[13]) | + SM(R92C_TXAGC_MCS02, power[14]) | + SM(R92C_TXAGC_MCS03, power[15])); + urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), + SM(R92C_TXAGC_MCS04, power[16]) | + SM(R92C_TXAGC_MCS05, power[17]) | + SM(R92C_TXAGC_MCS06, power[18]) | + SM(R92C_TXAGC_MCS07, power[19])); + urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), + SM(R92C_TXAGC_MCS08, power[20]) | + SM(R92C_TXAGC_MCS08, power[21]) | + SM(R92C_TXAGC_MCS10, power[22]) | + SM(R92C_TXAGC_MCS11, power[23])); + urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), + SM(R92C_TXAGC_MCS12, power[24]) | + SM(R92C_TXAGC_MCS13, power[25]) | + SM(R92C_TXAGC_MCS14, power[26]) | + SM(R92C_TXAGC_MCS15, power[27])); +} + +static void +urtwn_get_txpower(struct urtwn_softc *sc, int chain, u_int chan, u_int ht40m, + uint16_t power[URTWN_RIDX_COUNT]) +{ + struct r92c_rom *rom = &sc->rom; + uint16_t cckpow, ofdmpow, htpow, diff, maxpow; + const struct urtwn_txpwr *base; + int ridx, group; + + DPRINTFN(DBG_FN, ("%s: %s: chain=%d, chan=%d\n", + device_xname(sc->sc_dev), __func__, chain, chan)); + + /* Determine channel group. */ + if (chan <= 3) + group = 0; + else if (chan <= 9) + group = 1; + else + group = 2; + + /* Get original Tx power based on board type and RF chain. */ + if (!(sc->chip & URTWN_CHIP_92C)) { + if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) + base = &rtl8188ru_txagc[chain]; + else + base = &rtl8192cu_txagc[chain]; + } else + base = &rtl8192cu_txagc[chain]; + + memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); + if (sc->regulatory == 0) { + for (ridx = 0; ridx <= 3; ridx++) + power[ridx] = base->pwr[0][ridx]; + } + for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { + if (sc->regulatory == 3) { + power[ridx] = base->pwr[0][ridx]; + /* Apply vendor limits. */ + if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) + maxpow = rom->ht40_max_pwr[group]; + else + maxpow = rom->ht20_max_pwr[group]; + maxpow = (maxpow >> (chain * 4)) & 0xf; + if (power[ridx] > maxpow) + power[ridx] = maxpow; + } else if (sc->regulatory == 1) { + if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) + power[ridx] = base->pwr[group][ridx]; + } else if (sc->regulatory != 2) + power[ridx] = base->pwr[0][ridx]; + } + + /* Compute per-CCK rate Tx power. */ + cckpow = rom->cck_tx_pwr[chain][group]; + for (ridx = 0; ridx <= 3; ridx++) { + power[ridx] += cckpow; + if (power[ridx] > R92C_MAX_TX_PWR) + power[ridx] = R92C_MAX_TX_PWR; + } + + htpow = rom->ht40_1s_tx_pwr[chain][group]; + if (sc->ntxchains > 1) { + /* Apply reduction for 2 spatial streams. */ + diff = rom->ht40_2s_tx_pwr_diff[group]; + diff = (diff >> (chain * 4)) & 0xf; + htpow = (htpow > diff) ? htpow - diff : 0; + } + + /* Compute per-OFDM rate Tx power. */ + diff = rom->ofdm_tx_pwr_diff[group]; + diff = (diff >> (chain * 4)) & 0xf; + ofdmpow = htpow + diff; /* HT->OFDM correction. */ + for (ridx = 4; ridx <= 11; ridx++) { + power[ridx] += ofdmpow; + if (power[ridx] > R92C_MAX_TX_PWR) + power[ridx] = R92C_MAX_TX_PWR; + } + + /* Compute per-MCS Tx power. */ + if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { + diff = rom->ht20_tx_pwr_diff[group]; + diff = (diff >> (chain * 4)) & 0xf; + htpow += diff; /* HT40->HT20 correction. */ + } + for (ridx = 12; ridx <= 27; ridx++) { + power[ridx] += htpow; + if (power[ridx] > R92C_MAX_TX_PWR) + power[ridx] = R92C_MAX_TX_PWR; + } +#ifdef URTWN_DEBUG + if (urtwn_debug & DBG_RF) { + /* Dump per-rate Tx power values. */ + printf("%s: %s: Tx power for chain %d:\n", + device_xname(sc->sc_dev), __func__, chain); + for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) { + printf("%s: %s: Rate %d = %u\n", + device_xname(sc->sc_dev), __func__, ridx, + power[ridx]); + } + } +#endif +} + +static void +urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) +{ + uint16_t power[URTWN_RIDX_COUNT]; + int i; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + for (i = 0; i < sc->ntxchains; i++) { + /* Compute per-rate Tx power values. */ + urtwn_get_txpower(sc, i, chan, ht40m, power); + /* Write per-rate Tx power values to hardware. */ + urtwn_write_txpower(sc, i, power); + } +} + +static void +urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) +{ + struct ieee80211com *ic = &sc->sc_ic; + u_int chan; + int i; + + chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ + + DPRINTFN(DBG_FN, ("%s: %s: chan=%d\n", device_xname(sc->sc_dev), + __func__, chan)); + + /* Set Tx power for this new channel. */ + urtwn_set_txpower(sc, chan, ht40m); + + for (i = 0; i < sc->nrxchains; i++) { + urtwn_rf_write(sc, i, R92C_RF_CHNLBW, + RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); + } + urtwn_write_1(sc, R92C_BWOPMODE, + urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); + + urtwn_bb_write(sc, R92C_FPGA0_RFMOD, + urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); + urtwn_bb_write(sc, R92C_FPGA1_RFMOD, + urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); + + urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, + urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | + R92C_FPGA0_ANAPARAM2_CBW20); + + /* Select 20MHz bandwidth. */ + urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, + (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); +} + +static void +urtwn_iq_calib(struct urtwn_softc *sc, bool inited) +{ + + DPRINTFN(DBG_FN, ("%s: %s: inited=%d\n", device_xname(sc->sc_dev), + __func__, inited)); + + /* TODO */ +} + +static void +urtwn_lc_calib(struct urtwn_softc *sc) +{ + uint32_t rf_ac[2]; + uint8_t txmode; + int i; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); + if ((txmode & 0x70) != 0) { + /* Disable all continuous Tx. */ + urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); + + /* Set RF mode to standby mode. */ + for (i = 0; i < sc->nrxchains; i++) { + rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); + urtwn_rf_write(sc, i, R92C_RF_AC, + RW(rf_ac[i], R92C_RF_AC_MODE, + R92C_RF_AC_MODE_STANDBY)); + } + } else { + /* Block all Tx queues. */ + urtwn_write_1(sc, R92C_TXPAUSE, 0xff); + } + /* Start calibration. */ + urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, + urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); + + /* Give calibration the time to complete. */ + usbd_delay_ms(sc->sc_udev, 100); + + /* Restore configuration. */ + if ((txmode & 0x70) != 0) { + /* Restore Tx mode. */ + urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); + /* Restore RF mode. */ + for (i = 0; i < sc->nrxchains; i++) + urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); + } else { + /* Unblock all Tx queues. */ + urtwn_write_1(sc, R92C_TXPAUSE, 0x00); + } +} + +static void +urtwn_temp_calib(struct urtwn_softc *sc) +{ + int temp; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + if (sc->thcal_state == 0) { + /* Start measuring temperature. */ + DPRINTFN(DBG_RF, ("%s: %s: start measuring temperature\n", + device_xname(sc->sc_dev), __func__)); + urtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); + sc->thcal_state = 1; + return; + } + sc->thcal_state = 0; + + /* Read measured temperature. */ + temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; + DPRINTFN(DBG_RF, ("%s: %s: temperature=%d\n", device_xname(sc->sc_dev), + __func__, temp)); + if (temp == 0) /* Read failed, skip. */ + return; + + /* + * Redo LC calibration if temperature changed significantly since + * last calibration. + */ + if (sc->thcal_lctemp == 0) { + /* First LC calibration is performed in urtwn_init(). */ + sc->thcal_lctemp = temp; + } else if (abs(temp - sc->thcal_lctemp) > 1) { + DPRINTFN(DBG_RF, + ("%s: %s: LC calib triggered by temp: %d -> %d\n", + device_xname(sc->sc_dev), __func__, sc->thcal_lctemp, + temp)); + urtwn_lc_calib(sc); + /* Record temperature of last LC calibration. */ + sc->thcal_lctemp = temp; + } +} + +static int +urtwn_init(struct ifnet *ifp) +{ + struct urtwn_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + struct urtwn_rx_data *data; + uint32_t reg; + int i, error; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + mutex_enter(&sc->sc_task_mtx); + /* Init host async commands ring. */ + sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; + mutex_exit(&sc->sc_task_mtx); + + mutex_enter(&sc->sc_fwcmd_mtx); + /* Init firmware commands ring. */ + sc->fwcur = 0; + mutex_exit(&sc->sc_fwcmd_mtx); + + /* Allocate Tx/Rx buffers. */ + error = urtwn_alloc_rx_list(sc); + if (error != 0) { + aprint_error_dev(sc->sc_dev, + "could not allocate Rx buffers\n"); + goto fail; + } + error = urtwn_alloc_tx_list(sc); + if (error != 0) { + aprint_error_dev(sc->sc_dev, + "could not allocate Tx buffers\n"); + goto fail; + } + + /* Power on adapter. */ + error = urtwn_power_on(sc); + if (error != 0) + goto fail; + + /* Initialize DMA. */ + error = urtwn_dma_init(sc); + if (error != 0) + goto fail; + + /* Set info size in Rx descriptors (in 64-bit words). */ + urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); + + /* Init interrupts. */ + urtwn_write_4(sc, R92C_HISR, 0xffffffff); + urtwn_write_4(sc, R92C_HIMR, 0xffffffff); + + /* Set MAC address. */ + IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); + urtwn_write_region_1(sc, R92C_MACID, ic->ic_myaddr, + IEEE80211_ADDR_LEN); + + /* Set initial network type. */ + reg = urtwn_read_4(sc, R92C_CR); + reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); + urtwn_write_4(sc, R92C_CR, reg); + + urtwn_rxfilter_init(sc); + + /* Set response rate */ + reg = urtwn_read_4(sc, R92C_RRSR); + reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); + urtwn_write_4(sc, R92C_RRSR, reg); + + /* SIFS (used in NAV) */ + urtwn_write_2(sc, R92C_SPEC_SIFS, + SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); + + /* Set short/long retry limits. */ + urtwn_write_2(sc, R92C_RL, + SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); + + /* Initialize EDCA parameters. */ + urtwn_edca_init(sc); + + /* Setup rate fallback. */ + urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); + urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); + urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); + urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); + + urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, + urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | + R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); + /* Set ACK timeout. */ + urtwn_write_1(sc, R92C_ACKTO, 0x40); + + /* Setup USB aggregation. */ + /* Tx */ + reg = urtwn_read_4(sc, R92C_TDECTRL); + reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); + urtwn_write_4(sc, R92C_TDECTRL, reg); + /* Rx */ + urtwn_write_1(sc, R92C_TRXDMA_CTRL, + urtwn_read_1(sc, R92C_TRXDMA_CTRL) | + R92C_TRXDMA_CTRL_RXDMA_AGG_EN); + urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, + urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & + ~R92C_USB_SPECIAL_OPTION_AGG_EN); + urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); + urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); + + /* Initialize beacon parameters. */ + urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); + urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); + urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); + urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); + + /* Setup AMPDU aggregation. */ + urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ + urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); + urtwn_write_2(sc, 0x4ca, 0x0708); + + urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); + urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); + + /* Load 8051 microcode. */ + error = urtwn_load_firmware(sc); + if (error != 0) + goto fail; + SET(sc->sc_flags, URTWN_FLAG_FWREADY); + + /* Initialize MAC/BB/RF blocks. */ + urtwn_mac_init(sc); + urtwn_write_4(sc, R92C_RCR, + urtwn_read_4(sc, R92C_RCR) & ~R92C_RCR_ADF); + urtwn_bb_init(sc); + urtwn_rf_init(sc); + + /* Turn CCK and OFDM blocks on. */ + reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); + reg |= R92C_RFMOD_CCK_EN; + urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); + reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); + reg |= R92C_RFMOD_OFDM_EN; + urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); + + /* Clear per-station keys table. */ + urtwn_cam_init(sc); + + /* Enable hardware sequence numbering. */ + urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); + + /* Perform LO and IQ calibrations. */ + urtwn_iq_calib(sc, sc->iqk_inited); + sc->iqk_inited = true; + + /* Perform LC calibration. */ + urtwn_lc_calib(sc); + + /* Fix USB interference issue. */ + urtwn_write_1(sc, 0xfe40, 0xe0); + urtwn_write_1(sc, 0xfe41, 0x8d); + urtwn_write_1(sc, 0xfe42, 0x80); + urtwn_write_4(sc, 0x20c, 0xfd0320); + + urtwn_pa_bias_init(sc); + + if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R))) { + /* 1T1R */ + urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), + urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); + } + + /* Initialize GPIO setting. */ + urtwn_write_1(sc, R92C_GPIO_MUXCFG, + urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); + + /* Fix for lower temperature. */ + urtwn_write_1(sc, 0x15, 0xe9); + + /* Set default channel. */ + ic->ic_bss->ni_chan = ic->ic_ibss_chan; + urtwn_set_chan(sc, ic->ic_ibss_chan, IEEE80211_HTINFO_2NDCHAN_NONE); + + /* Queue Rx xfers. */ + for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { + data = &sc->rx_data[i]; + usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, + URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, + USBD_NO_TIMEOUT, urtwn_rxeof); + error = usbd_transfer(data->xfer); + if (__predict_false(error != USBD_NORMAL_COMPLETION && + error != USBD_IN_PROGRESS)) + goto fail; + } + + /* We're ready to go. */ + ifp->if_flags &= ~IFF_OACTIVE; + ifp->if_flags |= IFF_RUNNING; + + if (ic->ic_opmode == IEEE80211_M_MONITOR) + ieee80211_new_state(ic, IEEE80211_S_RUN, -1); + else + ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); + return (0); + + fail: + urtwn_stop(ifp, 1); + return (error); +} + +static void +urtwn_stop(struct ifnet *ifp, int disable) +{ + struct urtwn_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + int i, s; + + DPRINTFN(DBG_FN, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); + + sc->tx_timer = 0; + ifp->if_timer = 0; + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + + s = splusb(); + ieee80211_new_state(ic, IEEE80211_S_INIT, -1); + urtwn_wait_async(sc); + splx(s); + + callout_halt(&sc->sc_scan_to, NULL); + callout_halt(&sc->sc_calib_to, NULL); + + /* Abort Tx. */ + for (i = 0; i < R92C_MAX_EPOUT; i++) { + if (sc->tx_pipe[i] != NULL) + usbd_abort_pipe(sc->tx_pipe[i]); + } + + /* Stop Rx pipe. */ + usbd_abort_pipe(sc->rx_pipe); + + /* Free Tx/Rx buffers. */ + urtwn_free_tx_list(sc); + urtwn_free_rx_list(sc); +} diff --exclude=CVS --exclude='.#*' --exclude='obj.*' --exclude='makeBuild*' -uNr src.orig/sys/dev/usb/if_urtwn_data.h src/sys/dev/usb/if_urtwn_data.h --- src.orig/sys/dev/usb/if_urtwn_data.h 1970-01-01 09:00:00.000000000 +0900 +++ src/sys/dev/usb/if_urtwn_data.h 2012-01-21 00:16:55.000000000 +0900 @@ -0,0 +1,730 @@ +/* $NetBSD$ */ +/* $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ */ + +/*- + * Copyright (c) 2010 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * MAC initialization values. + */ +static const struct { + uint16_t reg; + uint8_t val; +} rtl8192cu_mac[] = { + { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, + { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, + { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, + { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, + { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, + { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, + { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, + { 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 }, + { 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff }, + { 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, + { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, + { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, + { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, + { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, + { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, + { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x40 }, { 0x547, 0x00 }, + { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55a, 0x02 }, + { 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a }, + { 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0e }, { 0x63e, 0x0a }, + { 0x63f, 0x0e }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 }, + { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, + { 0x70a, 0x65 }, { 0x70b, 0x87 } +}; + +/* + * Baseband initialization values. + */ +struct urtwn_bb_prog { + int count; + const uint16_t *regs; + const uint32_t *vals; + int agccount; + const uint32_t *agcvals; +}; + +/* + * RTL8192CU and RTL8192CE-VAU. + */ +static const uint16_t rtl8192ce_bb_regs[] = { + 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, + 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, + 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, + 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, + 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, + 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, + 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, + 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, + 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, + 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, + 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, + 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, + 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, + 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, + 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, + 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, + 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, + 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, + 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, + 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, + 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 +}; + +static const uint32_t rtl8192ce_bb_vals[] = { + 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, + 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, + 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, + 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, + 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, + 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, + 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, + 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, + 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, + 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, + 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, + 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, + 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, + 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, + 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, + 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, + 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, + 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, + 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, + 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, + 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, + 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, + 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, + 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, + 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, + 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, + 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, + 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, + 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, + 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, + 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, + 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, + 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, + 0x00000000, 0x00000300 +}; + +static const uint32_t rtl8192ce_agc_vals[] = { + 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, + 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, + 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, + 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, + 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, + 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, + 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, + 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, + 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, + 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, + 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, + 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, + 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, + 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, + 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, + 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, + 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, + 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, + 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, + 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, + 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, + 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, + 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, + 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, + 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, + 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, + 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, + 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, + 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, + 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, + 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, + 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e +}; + +static const struct urtwn_bb_prog rtl8192ce_bb_prog = { + __arraycount(rtl8192ce_bb_regs), + rtl8192ce_bb_regs, + rtl8192ce_bb_vals, + __arraycount(rtl8192ce_agc_vals), + rtl8192ce_agc_vals +}; + +/* + * RTL8188CU. + */ +static const uint32_t rtl8192cu_bb_vals[] = { + 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, + 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, + 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, + 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, + 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, + 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, + 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, + 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, + 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, + 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, + 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, + 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, + 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, + 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, + 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, + 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, + 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, + 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, + 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, + 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, + 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, + 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, + 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, + 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, + 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, + 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, + 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, + 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, + 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, + 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, + 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, + 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, + 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, + 0x00000000, 0x00000300 +}; + +static const struct urtwn_bb_prog rtl8192cu_bb_prog = { + __arraycount(rtl8192ce_bb_regs), + rtl8192ce_bb_regs, + rtl8192cu_bb_vals, + __arraycount(rtl8192ce_agc_vals), + rtl8192ce_agc_vals +}; + +/* + * RTL8188CE-VAU. + */ +static const uint32_t rtl8188ce_bb_vals[] = { + 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, + 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, + 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, + 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, + 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, + 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, + 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, + 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, + 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, + 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, + 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, + 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, + 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, + 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, + 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, + 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, + 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, + 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, + 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, + 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, + 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, + 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, + 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, + 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, + 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, + 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, + 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, + 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, + 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, + 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, + 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, + 0x00000000, 0x00000300 +}; + +static const uint32_t rtl8188ce_agc_vals[] = { + 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, + 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, + 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, + 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, + 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, + 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, + 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, + 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, + 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, + 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, + 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, + 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, + 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, + 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, + 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, + 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, + 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, + 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, + 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, + 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, + 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, + 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, + 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, + 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, + 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, + 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, + 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, + 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, + 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, + 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, + 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, + 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e +}; + +static const struct urtwn_bb_prog rtl8188ce_bb_prog = { + __arraycount(rtl8192ce_bb_regs), + rtl8192ce_bb_regs, + rtl8188ce_bb_vals, + __arraycount(rtl8188ce_agc_vals), + rtl8188ce_agc_vals +}; + +static const uint32_t rtl8188cu_bb_vals[] = { + 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, + 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, + 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, + 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, + 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, + 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, + 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, + 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, + 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, + 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, + 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, + 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, + 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, + 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, + 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, + 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, + 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, + 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, + 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, + 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, + 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, + 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, + 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, + 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, + 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, + 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, + 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, + 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, + 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, + 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, + 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, + 0x00000000, 0x00000300 +}; + +static const struct urtwn_bb_prog rtl8188cu_bb_prog = { + __arraycount(rtl8192ce_bb_regs), + rtl8192ce_bb_regs, + rtl8188cu_bb_vals, + __arraycount(rtl8188ce_agc_vals), + rtl8188ce_agc_vals +}; + +/* + * RTL8188RU. + */ +static const uint16_t rtl8188ru_bb_regs[] = { + 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, + 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, + 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, + 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, + 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, + 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, + 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, + 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, + 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, + 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, + 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, + 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, + 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, + 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, + 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, + 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, + 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, + 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, + 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, + 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, + 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 +}; + +static const uint32_t rtl8188ru_bb_vals[] = { + 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, + 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, + 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, + 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, + 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, + 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, + 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, + 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, + 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, + 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, + 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, + 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, + 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, + 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, + 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, + 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, + 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, + 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, + 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, + 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, + 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, + 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, + 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, + 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, + 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, + 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, + 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, + 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, + 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, + 0x31555448, 0x00000003, 0x00000000, 0x00000300 +}; + +static const uint32_t rtl8188ru_agc_vals[] = { + 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, + 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, + 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, + 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, + 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, + 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, + 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, + 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, + 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, + 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, + 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, + 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, + 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, + 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, + 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, + 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, + 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, + 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, + 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, + 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, + 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, + 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, + 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, + 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, + 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, + 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, + 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, + 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, + 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, + 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, + 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, + 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e +}; + +static const struct urtwn_bb_prog rtl8188ru_bb_prog = { + __arraycount(rtl8188ru_bb_regs), + rtl8188ru_bb_regs, + rtl8188ru_bb_vals, + __arraycount(rtl8188ru_agc_vals), + rtl8188ru_agc_vals +}; + +/* + * RF initialization values. + */ +struct urtwn_rf_prog { + int count; + const uint8_t *regs; + const uint32_t *vals; +}; + +/* + * RTL8192CU and RTL8192CE-VAU. + */ +static const uint8_t rtl8192ce_rf1_regs[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, + 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, + 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, + 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, + 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, + 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, + 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, + 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, + 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, + 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, + 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, + 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, + 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 +}; + +static const uint32_t rtl8192ce_rf1_vals[] = { + 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, + 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, + 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, + 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, + 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, + 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, + 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, + 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, + 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, + 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, + 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, + 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, + 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, + 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, + 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, + 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, + 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, + 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, + 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, + 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, + 0x30159 +}; + +static const uint8_t rtl8192ce_rf2_regs[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, + 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, + 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, + 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 +}; + +static const uint32_t rtl8192ce_rf2_vals[] = { + 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, + 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, + 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, + 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, + 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, + 0xe0330, 0xa0330, 0x60330, 0x20330 +}; + +static const struct urtwn_rf_prog rtl8192ce_rf_prog[] = { + { + __arraycount(rtl8192ce_rf1_regs), + rtl8192ce_rf1_regs, + rtl8192ce_rf1_vals + }, + { + __arraycount(rtl8192ce_rf2_regs), + rtl8192ce_rf2_regs, + rtl8192ce_rf2_vals + } +}; + +/* + * RTL8188CE-VAU. + */ +static const uint32_t rtl8188ce_rf_vals[] = { + 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, + 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, + 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, + 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, + 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, + 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, + 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, + 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, + 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, + 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, + 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, + 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, + 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, + 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, + 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, + 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, + 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, + 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, + 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, + 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, + 0x30159 +}; + +static const struct urtwn_rf_prog rtl8188ce_rf_prog[] = { + { + __arraycount(rtl8192ce_rf1_regs), + rtl8192ce_rf1_regs, + rtl8188ce_rf_vals + } +}; + + +/* + * RTL8188CU. + */ +static const uint32_t rtl8188cu_rf_vals[] = { + 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, + 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, + 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, + 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, + 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, + 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, + 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, + 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, + 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, + 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, + 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, + 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, + 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, + 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, + 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, + 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, + 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, + 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, + 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, + 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, + 0x30159 +}; + +static const struct urtwn_rf_prog rtl8188cu_rf_prog[] = { + { + __arraycount(rtl8192ce_rf1_regs), + rtl8192ce_rf1_regs, + rtl8188cu_rf_vals + } +}; + +/* + * RTL8188RU. + */ +static const uint32_t rtl8188ru_rf_vals[] = { + 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, + 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, + 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, + 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, + 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, + 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, + 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, + 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, + 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, + 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, + 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, + 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, + 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, + 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, + 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, + 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, + 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, + 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, + 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, + 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, + 0x30159 +}; + +static const struct urtwn_rf_prog rtl8188ru_rf_prog[] = { + { + __arraycount(rtl8192ce_rf1_regs), + rtl8192ce_rf1_regs, + rtl8188ru_rf_vals + } +}; + +struct urtwn_txpwr { + uint8_t pwr[3][28]; +}; + +/* + * Per RF chain/group/rate Tx gain values. + */ +static const struct urtwn_txpwr rtl8192cu_txagc[] = { + { { /* Chain 0. */ + { /* Group 0. */ + 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ + 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ + 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ + 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ + }, + { /* Group 1. */ + 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ + }, + { /* Group 2. */ + 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ + 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ + } + } }, + { { /* Chain 1. */ + { /* Group 0. */ + 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ + }, + { /* Group 1. */ + 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ + }, + { /* Group 2. */ + 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ + 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ + } + } } +}; + +static const struct urtwn_txpwr rtl8188ru_txagc[] = { + { { /* Chain 0. */ + { /* Group 0. */ + 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ + 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ + 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ + 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ + }, + { /* Group 1. */ + 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ + }, + { /* Group 2. */ + 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ + } + } } +}; diff --exclude=CVS --exclude='.#*' --exclude='obj.*' --exclude='makeBuild*' -uNr src.orig/sys/dev/usb/if_urtwnreg.h src/sys/dev/usb/if_urtwnreg.h --- src.orig/sys/dev/usb/if_urtwnreg.h 1970-01-01 09:00:00.000000000 +0900 +++ src/sys/dev/usb/if_urtwnreg.h 2012-01-25 21:40:14.000000000 +0900 @@ -0,0 +1,1008 @@ +/* $NetBSD$ */ +/* $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ */ + +/*- + * Copyright (c) 2010 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define R92C_MAX_CHAINS 2 + +/* Maximum number of output pipes is 3. */ +#define R92C_MAX_EPOUT 3 + +#define R92C_MAX_TX_PWR 0x3f + +#define R92C_PUBQ_NPAGES 231 +#define R92C_TXPKTBUF_COUNT 256 +#define R92C_TX_PAGE_COUNT 248 +#define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) + +#define R92C_H2C_NBOX 4 + +/* USB Requests. */ +#define R92C_REQ_REGS 0x05 + +/* + * MAC registers. + */ +/* System Configuration. */ +#define R92C_SYS_ISO_CTRL 0x000 +#define R92C_SYS_FUNC_EN 0x002 +#define R92C_APS_FSMCO 0x004 +#define R92C_SYS_CLKR 0x008 +#define R92C_AFE_MISC 0x010 +#define R92C_SPS0_CTRL 0x011 +#define R92C_SPS_OCP_CFG 0x018 +#define R92C_RSV_CTRL 0x01c +#define R92C_RF_CTRL 0x01f +#define R92C_LDOA15_CTRL 0x020 +#define R92C_LDOV12D_CTRL 0x021 +#define R92C_LDOHCI12_CTRL 0x022 +#define R92C_LPLDO_CTRL 0x023 +#define R92C_AFE_XTAL_CTRL 0x024 +#define R92C_AFE_PLL_CTRL 0x028 +#define R92C_EFUSE_CTRL 0x030 +#define R92C_EFUSE_TEST 0x034 +#define R92C_PWR_DATA 0x038 +#define R92C_CAL_TIMER 0x03c +#define R92C_ACLK_MON 0x03e +#define R92C_GPIO_MUXCFG 0x040 +#define R92C_GPIO_IO_SEL 0x042 +#define R92C_MAC_PINMUX_CFG 0x043 +#define R92C_GPIO_PIN_CTRL 0x044 +#define R92C_GPIO_INTM 0x048 +#define R92C_LEDCFG0 0x04c +#define R92C_LEDCFG1 0x04d +#define R92C_LEDCFG2 0x04e +#define R92C_LEDCFG3 0x04f +#define R92C_FSIMR 0x050 +#define R92C_FSISR 0x054 +#define R92C_HSIMR 0x058 +#define R92C_HSISR 0x05c +#define R92C_MCUFWDL 0x080 +#define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) +#define R92C_BIST_SCAN 0x0d0 +#define R92C_BIST_RPT 0x0d4 +#define R92C_BIST_ROM_RPT 0x0d8 +#define R92C_USB_SIE_INTF 0x0e0 +#define R92C_PCIE_MIO_INTF 0x0e4 +#define R92C_PCIE_MIO_INTD 0x0e8 +#define R92C_HPON_FSM 0x0ec +#define R92C_SYS_CFG 0x0f0 +/* MAC General Configuration. */ +#define R92C_CR 0x100 +#define R92C_PBP 0x104 +#define R92C_TRXDMA_CTRL 0x10c +#define R92C_TRXFF_BNDY 0x114 +#define R92C_TRXFF_STATUS 0x118 +#define R92C_RXFF_PTR 0x11c +#define R92C_HIMR 0x120 +#define R92C_HISR 0x124 +#define R92C_HIMRE 0x128 +#define R92C_HISRE 0x12c +#define R92C_CPWM 0x12f +#define R92C_FWIMR 0x130 +#define R92C_FWISR 0x134 +#define R92C_PKTBUF_DBG_CTRL 0x140 +#define R92C_PKTBUF_DBG_DATA_L 0x144 +#define R92C_PKTBUF_DBG_DATA_H 0x148 +#define R92C_TC0_CTRL(i) (0x150 + (i) * 4) +#define R92C_TCUNIT_BASE 0x164 +#define R92C_MBIST_START 0x174 +#define R92C_MBIST_DONE 0x178 +#define R92C_MBIST_FAIL 0x17c +#define R92C_C2HEVT_MSG_NORMAL 0x1a0 +#define R92C_C2HEVT_MSG_TEST 0x1b8 +#define R92C_C2HEVT_CLEAR 0x1bf +#define R92C_MCUTST_1 0x1c0 +#define R92C_FMETHR 0x1c8 +#define R92C_HMETFR 0x1cc +#define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) +#define R92C_LLT_INIT 0x1e0 +#define R92C_BB_ACCESS_CTRL 0x1e8 +#define R92C_BB_ACCESS_DATA 0x1ec +/* Tx DMA Configuration. */ +#define R92C_RQPN 0x200 +#define R92C_FIFOPAGE 0x204 +#define R92C_TDECTRL 0x208 +#define R92C_TXDMA_OFFSET_CHK 0x20c +#define R92C_TXDMA_STATUS 0x210 +#define R92C_RQPN_NPQ 0x214 +/* Rx DMA Configuration. */ +#define R92C_RXDMA_AGG_PG_TH 0x280 +#define R92C_RXPKT_NUM 0x284 +#define R92C_RXDMA_STATUS 0x288 +/* Protocol Configuration. */ +#define R92C_FWHW_TXQ_CTRL 0x420 +#define R92C_HWSEQ_CTRL 0x423 +#define R92C_TXPKTBUF_BCNQ_BDNY 0x424 +#define R92C_TXPKTBUF_MGQ_BDNY 0x425 +#define R92C_SPEC_SIFS 0x428 +#define R92C_RL 0x42a +#define R92C_DARFRC 0x430 +#define R92C_RARFRC 0x438 +#define R92C_RRSR 0x440 +#define R92C_ARFR(i) (0x444 + (i) * 4) +#define R92C_AGGLEN_LMT 0x458 +#define R92C_AMPDU_MIN_SPACE 0x45c +#define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d +#define R92C_FAST_EDCA_CTRL 0x460 +#define R92C_RD_RESP_PKT_TH 0x463 +#define R92C_INIRTS_RATE_SEL 0x480 +#define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) +#define R92C_PROT_MODE_CTRL 0x4c8 +#define R92C_BAR_MODE_CTRL 0x4cc +/* EDCA Configuration. */ +#define R92C_EDCA_VO_PARAM 0x500 +#define R92C_EDCA_VI_PARAM 0x504 +#define R92C_EDCA_BE_PARAM 0x508 +#define R92C_EDCA_BK_PARAM 0x50c +#define R92C_BCNTCFG 0x510 +#define R92C_PIFS 0x512 +#define R92C_RDG_PIFS 0x513 +#define R92C_SIFS_CCK 0x514 +#define R92C_SIFS_OFDM 0x516 +#define R92C_AGGR_BREAK_TIME 0x51a +#define R92C_SLOT 0x51b +#define R92C_TX_PTCL_CTRL 0x520 +#define R92C_TXPAUSE 0x522 +#define R92C_DIS_TXREQ_CLR 0x523 +#define R92C_RD_CTRL 0x524 +#define R92C_TBTT_PROHIBIT 0x540 +#define R92C_RD_NAV_NXT 0x544 +#define R92C_NAV_PROT_LEN 0x546 +#define R92C_BCN_CTRL 0x550 +#define R92C_USTIME_TSF 0x551 +#define R92C_MBID_NUM 0x552 +#define R92C_DUAL_TSF_RST 0x553 +#define R92C_BCN_INTERVAL 0x554 +#define R92C_DRVERLYINT 0x558 +#define R92C_BCNDMATIM 0x559 +#define R92C_ATIMWND 0x55a +#define R92C_BCN_MAX_ERR 0x55d +#define R92C_RXTSF_OFFSET_CCK 0x55e +#define R92C_RXTSF_OFFSET_OFDM 0x55f +#define R92C_TSFTR 0x560 +#define R92C_INIT_TSFTR 0x564 +#define R92C_PSTIMER 0x580 +#define R92C_TIMER0 0x584 +#define R92C_TIMER1 0x588 +#define R92C_ACMHWCTRL 0x5c0 +#define R92C_ACMRSTCTRL 0x5c1 +#define R92C_ACMAVG 0x5c2 +#define R92C_VO_ADMTIME 0x5c4 +#define R92C_VI_ADMTIME 0x5c6 +#define R92C_BE_ADMTIME 0x5c8 +#define R92C_EDCA_RANDOM_GEN 0x5cc +#define R92C_SCH_TXCMD 0x5d0 +/* WMAC Configuration. */ +#define R92C_APSD_CTRL 0x600 +#define R92C_BWOPMODE 0x603 +#define R92C_RCR 0x608 +#define R92C_RX_DRVINFO_SZ 0x60f +#define R92C_MACID 0x610 +#define R92C_BSSID 0x618 +#define R92C_MAR 0x620 +#define R92C_MAC_SPEC_SIFS 0x63a +#define R92C_R2T_SIFS 0x63c +#define R92C_T2T_SIFS 0x63e +#define R92C_ACKTO 0x640 +#define R92C_CAMCMD 0x670 +#define R92C_CAMWRITE 0x674 +#define R92C_CAMREAD 0x678 +#define R92C_CAMDBG 0x67c +#define R92C_SECCFG 0x680 +#define R92C_RXFLTMAP0 0x6a0 +#define R92C_RXFLTMAP1 0x6a2 +#define R92C_RXFLTMAP2 0x6a4 + +/* Bits for R92C_SYS_ISO_CTRL. */ +#define R92C_SYS_ISO_CTRL_MD2PP 0x0001 +#define R92C_SYS_ISO_CTRL_UA2USB 0x0002 +#define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 +#define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 +#define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 +#define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 +#define R92C_SYS_ISO_CTRL_DIOP 0x0040 +#define R92C_SYS_ISO_CTRL_DIOE 0x0080 +#define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 +#define R92C_SYS_ISO_CTRL_DIOR 0x0200 +#define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 +#define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 + +/* Bits for R92C_SYS_FUNC_EN. */ +#define R92C_SYS_FUNC_EN_BBRSTB 0x0001 +#define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 +#define R92C_SYS_FUNC_EN_USBA 0x0004 +#define R92C_SYS_FUNC_EN_UPLL 0x0008 +#define R92C_SYS_FUNC_EN_USBD 0x0010 +#define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 +#define R92C_SYS_FUNC_EN_PCIEA 0x0040 +#define R92C_SYS_FUNC_EN_PPLL 0x0080 +#define R92C_SYS_FUNC_EN_PCIED 0x0100 +#define R92C_SYS_FUNC_EN_DIOE 0x0200 +#define R92C_SYS_FUNC_EN_CPUEN 0x0400 +#define R92C_SYS_FUNC_EN_DCORE 0x0800 +#define R92C_SYS_FUNC_EN_ELDR 0x1000 +#define R92C_SYS_FUNC_EN_DIO_RF 0x2000 +#define R92C_SYS_FUNC_EN_HWPDN 0x4000 +#define R92C_SYS_FUNC_EN_MREGEN 0x8000 + +/* Bits for R92C_APS_FSMCO. */ +#define R92C_APS_FSMCO_PFM_LDALL 0x00000001 +#define R92C_APS_FSMCO_PFM_ALDN 0x00000002 +#define R92C_APS_FSMCO_PFM_LDKP 0x00000004 +#define R92C_APS_FSMCO_PFM_WOWL 0x00000008 +#define R92C_APS_FSMCO_PDN_EN 0x00000010 +#define R92C_APS_FSMCO_PDN_PL 0x00000020 +#define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 +#define R92C_APS_FSMCO_APFM_OFF 0x00000200 +#define R92C_APS_FSMCO_APFM_RSM 0x00000400 +#define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 +#define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 +#define R92C_APS_FSMCO_APDM_MAC 0x00002000 +#define R92C_APS_FSMCO_APDM_HOST 0x00004000 +#define R92C_APS_FSMCO_APDM_HPDN 0x00008000 +#define R92C_APS_FSMCO_RDY_MACON 0x00010000 +#define R92C_APS_FSMCO_SUS_HOST 0x00020000 +#define R92C_APS_FSMCO_ROP_ALD 0x00100000 +#define R92C_APS_FSMCO_ROP_PWR 0x00200000 +#define R92C_APS_FSMCO_ROP_SPS 0x00400000 +#define R92C_APS_FSMCO_SOP_MRST 0x02000000 +#define R92C_APS_FSMCO_SOP_FUSE 0x04000000 +#define R92C_APS_FSMCO_SOP_ABG 0x08000000 +#define R92C_APS_FSMCO_SOP_AMB 0x10000000 +#define R92C_APS_FSMCO_SOP_RCK 0x20000000 +#define R92C_APS_FSMCO_SOP_A8M 0x40000000 +#define R92C_APS_FSMCO_XOP_BTCK 0x80000000 + +/* Bits for R92C_SYS_CLKR. */ +#define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 +#define R92C_SYS_CLKR_ANA8M 0x00000002 +#define R92C_SYS_CLKR_MACSLP 0x00000010 +#define R92C_SYS_CLKR_LOADER_EN 0x00000020 +#define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 +#define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 +#define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 +#define R92C_SYS_CLKR_SEC_EN 0x00000400 +#define R92C_SYS_CLKR_MAC_EN 0x00000800 +#define R92C_SYS_CLKR_SYS_EN 0x00001000 +#define R92C_SYS_CLKR_RING_EN 0x00002000 + +/* Bits for R92C_RF_CTRL. */ +#define R92C_RF_CTRL_EN 0x01 +#define R92C_RF_CTRL_RSTB 0x02 +#define R92C_RF_CTRL_SDMRSTB 0x04 + +/* Bits for R92C_LDOV12D_CTRL. */ +#define R92C_LDOV12D_CTRL_LDV12_EN 0x01 + +/* Bits for R92C_EFUSE_CTRL. */ +#define R92C_EFUSE_CTRL_DATA_M 0x000000ff +#define R92C_EFUSE_CTRL_DATA_S 0 +#define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 +#define R92C_EFUSE_CTRL_ADDR_S 8 +#define R92C_EFUSE_CTRL_VALID 0x80000000 + +/* Bits for R92C_GPIO_MUXCFG. */ +#define R92C_GPIO_MUXCFG_ENBT 0x0020 + +/* Bits for R92C_LEDCFG0. */ +#define R92C_LEDCFG0_DIS 0x08 + +/* Bits for R92C_MCUFWDL. */ +#define R92C_MCUFWDL_EN 0x00000001 +#define R92C_MCUFWDL_RDY 0x00000002 +#define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 +#define R92C_MCUFWDL_MACINI_RDY 0x00000008 +#define R92C_MCUFWDL_BBINI_RDY 0x00000010 +#define R92C_MCUFWDL_RFINI_RDY 0x00000020 +#define R92C_MCUFWDL_WINTINI_RDY 0x00000040 +#define R92C_MCUFWDL_PAGE_M 0x00070000 +#define R92C_MCUFWDL_PAGE_S 16 +#define R92C_MCUFWDL_CPRST 0x00800000 + +/* Bits for R92C_HPON_FSM. */ +#define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 +#define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 +#define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 + +/* Bits for R92C_SYS_CFG. */ +#define R92C_SYS_CFG_XCLK_VLD 0x00000001 +#define R92C_SYS_CFG_ACLK_VLD 0x00000002 +#define R92C_SYS_CFG_UCLK_VLD 0x00000004 +#define R92C_SYS_CFG_PCLK_VLD 0x00000008 +#define R92C_SYS_CFG_PCIRSTB 0x00000010 +#define R92C_SYS_CFG_V15_VLD 0x00000020 +#define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 +#define R92C_SYS_CFG_SIC_IDLE 0x00000100 +#define R92C_SYS_CFG_BD_MAC2 0x00000200 +#define R92C_SYS_CFG_BD_MAC1 0x00000400 +#define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 +#define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 +#define R92C_SYS_CFG_CHIP_VER_RTL_S 12 +#define R92C_SYS_CFG_BT_FUNC 0x00010000 +#define R92C_SYS_CFG_VENDOR_UMC 0x00080000 +#define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 +#define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 +#define R92C_SYS_CFG_TRP_BT_EN 0x01000000 +#define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 +#define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 +#define R92C_SYS_CFG_TYPE_92C 0x08000000 + +/* Bits for R92C_CR. */ +#define R92C_CR_HCI_TXDMA_EN 0x00000001 +#define R92C_CR_HCI_RXDMA_EN 0x00000002 +#define R92C_CR_TXDMA_EN 0x00000004 +#define R92C_CR_RXDMA_EN 0x00000008 +#define R92C_CR_PROTOCOL_EN 0x00000010 +#define R92C_CR_SCHEDULE_EN 0x00000020 +#define R92C_CR_MACTXEN 0x00000040 +#define R92C_CR_MACRXEN 0x00000080 +#define R92C_CR_ENSEC 0x00000200 +#define R92C_CR_NETTYPE_S 16 +#define R92C_CR_NETTYPE_M 0x00030000 +#define R92C_CR_NETTYPE_NOLINK 0 +#define R92C_CR_NETTYPE_ADHOC 1 +#define R92C_CR_NETTYPE_INFRA 2 +#define R92C_CR_NETTYPE_AP 3 + +/* Bits for R92C_PBP. */ +#define R92C_PBP_PSRX_M 0x0f +#define R92C_PBP_PSRX_S 0 +#define R92C_PBP_PSTX_M 0xf0 +#define R92C_PBP_PSTX_S 4 +#define R92C_PBP_64 0 +#define R92C_PBP_128 1 +#define R92C_PBP_256 2 +#define R92C_PBP_512 3 +#define R92C_PBP_1024 4 + +/* Bits for R92C_TRXDMA_CTRL. */ +#define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 +#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 +#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 +#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 +#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 +#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 +#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 +#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 +#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 +#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 +#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 +#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 +#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 +#define R92C_TRXDMA_CTRL_QUEUE_LOW 1 +#define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 +#define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 +#define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 +/* Shortcuts. */ +#define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 +#define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 +#define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 +#define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 +#define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 +#define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 + +/* Bits for R92C_LLT_INIT. */ +#define R92C_LLT_INIT_DATA_M 0x000000ff +#define R92C_LLT_INIT_DATA_S 0 +#define R92C_LLT_INIT_ADDR_M 0x0000ff00 +#define R92C_LLT_INIT_ADDR_S 8 +#define R92C_LLT_INIT_OP_M 0xc0000000 +#define R92C_LLT_INIT_OP_S 30 +#define R92C_LLT_INIT_OP_NO_ACTIVE 0 +#define R92C_LLT_INIT_OP_WRITE 1 + +/* Bits for R92C_RQPN. */ +#define R92C_RQPN_HPQ_M 0x000000ff +#define R92C_RQPN_HPQ_S 0 +#define R92C_RQPN_LPQ_M 0x0000ff00 +#define R92C_RQPN_LPQ_S 8 +#define R92C_RQPN_PUBQ_M 0x00ff0000 +#define R92C_RQPN_PUBQ_S 16 +#define R92C_RQPN_LD 0x80000000 + +/* Bits for R92C_TDECTRL. */ +#define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f +#define R92C_TDECTRL_BLK_DESC_NUM_S 4 + +/* Bits for R92C_FWHW_TXQ_CTRL. */ +#define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 + +/* Bits for R92C_SPEC_SIFS. */ +#define R92C_SPEC_SIFS_CCK_M 0x00ff +#define R92C_SPEC_SIFS_CCK_S 0 +#define R92C_SPEC_SIFS_OFDM_M 0xff00 +#define R92C_SPEC_SIFS_OFDM_S 8 + +/* Bits for R92C_RL. */ +#define R92C_RL_LRL_M 0x003f +#define R92C_RL_LRL_S 0 +#define R92C_RL_SRL_M 0x3f00 +#define R92C_RL_SRL_S 8 + +/* Bits for R92C_RRSR. */ +#define R92C_RRSR_RATE_BITMAP_M 0x000fffff +#define R92C_RRSR_RATE_BITMAP_S 0 +#define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 +#define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 +#define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 +#define R92C_RRSR_SHORT 0x00800000 + +/* Bits for R92C_EDCA_XX_PARAM. */ +#define R92C_EDCA_PARAM_AIFS_M 0x000000ff +#define R92C_EDCA_PARAM_AIFS_S 0 +#define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 +#define R92C_EDCA_PARAM_ECWMIN_S 8 +#define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 +#define R92C_EDCA_PARAM_ECWMAX_S 12 +#define R92C_EDCA_PARAM_TXOP_M 0xffff0000 +#define R92C_EDCA_PARAM_TXOP_S 16 + +/* Bits for R92C_BCN_CTRL. */ +#define R92C_BCN_CTRL_EN_MBSSID 0x02 +#define R92C_BCN_CTRL_TXBCN_RPT 0x04 +#define R92C_BCN_CTRL_EN_BCN 0x08 +#define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 + +/* Bits for R92C_APSD_CTRL. */ +#define R92C_APSD_CTRL_OFF 0x40 +#define R92C_APSD_CTRL_OFF_STATUS 0x80 + +/* Bits for R92C_BWOPMODE. */ +#define R92C_BWOPMODE_11J 0x01 +#define R92C_BWOPMODE_5G 0x02 +#define R92C_BWOPMODE_20MHZ 0x04 + +/* Bits for R92C_RCR. */ +#define R92C_RCR_AAP 0x00000001 +#define R92C_RCR_APM 0x00000002 +#define R92C_RCR_AM 0x00000004 +#define R92C_RCR_AB 0x00000008 +#define R92C_RCR_ADD3 0x00000010 +#define R92C_RCR_APWRMGT 0x00000020 +#define R92C_RCR_CBSSID_DATA 0x00000040 +#define R92C_RCR_CBSSID_BCN 0x00000080 +#define R92C_RCR_ACRC32 0x00000100 +#define R92C_RCR_AICV 0x00000200 +#define R92C_RCR_ADF 0x00000800 +#define R92C_RCR_ACF 0x00001000 +#define R92C_RCR_AMF 0x00002000 +#define R92C_RCR_HTC_LOC_CTRL 0x00004000 +#define R92C_RCR_MFBEN 0x00400000 +#define R92C_RCR_LSIGEN 0x00800000 +#define R92C_RCR_ENMBID 0x01000000 +#define R92C_RCR_APP_BA_SSN 0x08000000 +#define R92C_RCR_APP_PHYSTS 0x10000000 +#define R92C_RCR_APP_ICV 0x20000000 +#define R92C_RCR_APP_MIC 0x40000000 +#define R92C_RCR_APPFCS 0x80000000 + +/* Bits for R92C_CAMCMD. */ +#define R92C_CAMCMD_ADDR_M 0x0000ffff +#define R92C_CAMCMD_ADDR_S 0 +#define R92C_CAMCMD_WRITE 0x00010000 +#define R92C_CAMCMD_CLR 0x40000000 +#define R92C_CAMCMD_POLLING 0x80000000 + + +/* + * Baseband registers. + */ +#define R92C_FPGA0_RFMOD 0x800 +#define R92C_FPGA0_TXINFO 0x804 +#define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) +#define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) +#define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) +#define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) +#define R92C_TXAGC_A_CCK1_MCS32 0xe08 +#define R92C_FPGA0_XA_HSSIPARAM1 0x820 +#define R92C_TXAGC_B_CCK1_55_MCS32 0x838 +#define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c +#define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) +#define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) +#define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) +#define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) +#define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) +#define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) +#define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) +#define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) +#define R92C_FPGA0_ANAPARAM2 0x884 +#define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) +#define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) +#define R92C_FPGA1_RFMOD 0x900 +#define R92C_FPGA1_TXINFO 0x90c +#define R92C_CCK0_SYSTEM 0xa00 +#define R92C_CCK0_AFESETTING 0xa04 +#define R92C_OFDM0_TRXPATHENA 0xc04 +#define R92C_OFDM0_TRMUXPAR 0xc08 +#define R92C_OFDM0_XARXIQIMBALANCE 0xc14 +#define R92C_OFDM0_ECCATHRESHOLD 0xc4c +#define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) +#define R92C_OFDM0_AGCPARAM1 0xc70 +#define R92C_OFDM0_AGCRSSITABLE 0xc78 +#define R92C_OFDM0_HTSTFAGC 0xc7c +#define R92C_OFDM0_XATXIQIMBALANCE 0xc80 +#define R92C_OFDM0_XBTXIQIMBALANCE 0xc88 +#define R92C_OFDM0_XCTXIQIMBALANCE 0xc90 +#define R92C_OFDM0_XCTXAFE 0xc94 +#define R92C_OFDM0_XDTXAFE 0xc9c +#define R92C_OFDM0_RXIQEXTANTA 0xca0 +#define R92C_OFDM1_LSTF 0xd00 + +/* Bits for R92C_FPGA[01]_RFMOD. */ +#define R92C_RFMOD_40MHZ 0x00000001 +#define R92C_RFMOD_JAPAN 0x00000002 +#define R92C_RFMOD_CCK_TXSC 0x00000030 +#define R92C_RFMOD_CCK_EN 0x01000000 +#define R92C_RFMOD_OFDM_EN 0x02000000 + +/* Bits for R92C_HSSI_PARAM1(i). */ +#define R92C_HSSI_PARAM1_PI 0x00000100 + +/* Bits for R92C_HSSI_PARAM2(i). */ +#define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 +#define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 +#define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 +#define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 +#define R92C_HSSI_PARAM2_READ_ADDR_S 23 +#define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 + +/* Bits for R92C_TXAGC_A_CCK1_MCS32. */ +#define R92C_TXAGC_A_CCK1_M 0x0000ff00 +#define R92C_TXAGC_A_CCK1_S 8 + +/* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ +#define R92C_TXAGC_B_CCK11_M 0x000000ff +#define R92C_TXAGC_B_CCK11_S 0 +#define R92C_TXAGC_A_CCK2_M 0x0000ff00 +#define R92C_TXAGC_A_CCK2_S 8 +#define R92C_TXAGC_A_CCK55_M 0x00ff0000 +#define R92C_TXAGC_A_CCK55_S 16 +#define R92C_TXAGC_A_CCK11_M 0xff000000 +#define R92C_TXAGC_A_CCK11_S 24 + +/* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ +#define R92C_TXAGC_B_CCK1_M 0x0000ff00 +#define R92C_TXAGC_B_CCK1_S 8 +#define R92C_TXAGC_B_CCK2_M 0x00ff0000 +#define R92C_TXAGC_B_CCK2_S 16 +#define R92C_TXAGC_B_CCK55_M 0xff000000 +#define R92C_TXAGC_B_CCK55_S 24 + +/* Bits for R92C_TXAGC_RATE18_06(x). */ +#define R92C_TXAGC_RATE06_M 0x000000ff +#define R92C_TXAGC_RATE06_S 0 +#define R92C_TXAGC_RATE09_M 0x0000ff00 +#define R92C_TXAGC_RATE09_S 8 +#define R92C_TXAGC_RATE12_M 0x00ff0000 +#define R92C_TXAGC_RATE12_S 16 +#define R92C_TXAGC_RATE18_M 0xff000000 +#define R92C_TXAGC_RATE18_S 24 + +/* Bits for R92C_TXAGC_RATE54_24(x). */ +#define R92C_TXAGC_RATE24_M 0x000000ff +#define R92C_TXAGC_RATE24_S 0 +#define R92C_TXAGC_RATE36_M 0x0000ff00 +#define R92C_TXAGC_RATE36_S 8 +#define R92C_TXAGC_RATE48_M 0x00ff0000 +#define R92C_TXAGC_RATE48_S 16 +#define R92C_TXAGC_RATE54_M 0xff000000 +#define R92C_TXAGC_RATE54_S 24 + +/* Bits for R92C_TXAGC_MCS03_MCS00(x). */ +#define R92C_TXAGC_MCS00_M 0x000000ff +#define R92C_TXAGC_MCS00_S 0 +#define R92C_TXAGC_MCS01_M 0x0000ff00 +#define R92C_TXAGC_MCS01_S 8 +#define R92C_TXAGC_MCS02_M 0x00ff0000 +#define R92C_TXAGC_MCS02_S 16 +#define R92C_TXAGC_MCS03_M 0xff000000 +#define R92C_TXAGC_MCS03_S 24 + +/* Bits for R92C_TXAGC_MCS07_MCS04(x). */ +#define R92C_TXAGC_MCS04_M 0x000000ff +#define R92C_TXAGC_MCS04_S 0 +#define R92C_TXAGC_MCS05_M 0x0000ff00 +#define R92C_TXAGC_MCS05_S 8 +#define R92C_TXAGC_MCS06_M 0x00ff0000 +#define R92C_TXAGC_MCS06_S 16 +#define R92C_TXAGC_MCS07_M 0xff000000 +#define R92C_TXAGC_MCS07_S 24 + +/* Bits for R92C_TXAGC_MCS11_MCS08(x). */ +#define R92C_TXAGC_MCS08_M 0x000000ff +#define R92C_TXAGC_MCS08_S 0 +#define R92C_TXAGC_MCS09_M 0x0000ff00 +#define R92C_TXAGC_MCS09_S 8 +#define R92C_TXAGC_MCS10_M 0x00ff0000 +#define R92C_TXAGC_MCS10_S 16 +#define R92C_TXAGC_MCS11_M 0xff000000 +#define R92C_TXAGC_MCS11_S 24 + +/* Bits for R92C_TXAGC_MCS15_MCS12(x). */ +#define R92C_TXAGC_MCS12_M 0x000000ff +#define R92C_TXAGC_MCS12_S 0 +#define R92C_TXAGC_MCS13_M 0x0000ff00 +#define R92C_TXAGC_MCS13_S 8 +#define R92C_TXAGC_MCS14_M 0x00ff0000 +#define R92C_TXAGC_MCS14_S 16 +#define R92C_TXAGC_MCS15_M 0xff000000 +#define R92C_TXAGC_MCS15_S 24 + +/* Bits for R92C_LSSI_PARAM(i). */ +#define R92C_LSSI_PARAM_DATA_M 0x000fffff +#define R92C_LSSI_PARAM_DATA_S 0 +#define R92C_LSSI_PARAM_ADDR_M 0x03f00000 +#define R92C_LSSI_PARAM_ADDR_S 20 + +/* Bits for R92C_FPGA0_ANAPARAM2. */ +#define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 + +/* Bits for R92C_LSSI_READBACK(i). */ +#define R92C_LSSI_READBACK_DATA_M 0x000fffff +#define R92C_LSSI_READBACK_DATA_S 0 + +/* Bits for R92C_OFDM0_AGCCORE1(i). */ +#define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f +#define R92C_OFDM0_AGCCORE1_GAIN_S 0 + + +/* + * USB registers. + */ +#define R92C_USB_INFO 0xfe17 +#define R92C_USB_SPECIAL_OPTION 0xfe55 +#define R92C_USB_HCPWM 0xfe57 +#define R92C_USB_HRPWM 0xfe58 +#define R92C_USB_DMA_AGG_TO 0xfe5b +#define R92C_USB_AGG_TO 0xfe5c +#define R92C_USB_AGG_TH 0xfe5d +#define R92C_USB_VID 0xfe60 +#define R92C_USB_PID 0xfe62 +#define R92C_USB_OPTIONAL 0xfe64 +#define R92C_USB_EP 0xfe65 +#define R92C_USB_PHY 0xfe68 +#define R92C_USB_MAC_ADDR 0xfe70 +#define R92C_USB_STRING 0xfe80 + +/* Bits for R92C_USB_SPECIAL_OPTION. */ +#define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 + +/* Bits for R92C_USB_EP. */ +#define R92C_USB_EP_HQ_M 0x000f +#define R92C_USB_EP_HQ_S 0 +#define R92C_USB_EP_NQ_M 0x00f0 +#define R92C_USB_EP_NQ_S 4 +#define R92C_USB_EP_LQ_M 0x0f00 +#define R92C_USB_EP_LQ_S 8 + +/* Bits for R92C_RD_CTRL. */ +#define R92C_RD_CTRL_DIS_EDCA_CNT_DWN __BIT(11) + +/* + * Firmware base address. + */ +#define R92C_FW_START_ADDR 0x1000 +#define R92C_FW_PAGE_SIZE 4096 + + +/* + * RF (6052) registers. + */ +#define R92C_RF_AC 0x00 +#define R92C_RF_IQADJ_G(i) (0x01 + (i)) +#define R92C_RF_POW_TRSW 0x05 +#define R92C_RF_GAIN_RX 0x06 +#define R92C_RF_GAIN_TX 0x07 +#define R92C_RF_TXM_IDAC 0x08 +#define R92C_RF_BS_IQGEN 0x0f +#define R92C_RF_MODE1 0x10 +#define R92C_RF_MODE2 0x11 +#define R92C_RF_RX_AGC_HP 0x12 +#define R92C_RF_TX_AGC 0x13 +#define R92C_RF_BIAS 0x14 +#define R92C_RF_IPA 0x15 +#define R92C_RF_POW_ABILITY 0x17 +#define R92C_RF_CHNLBW 0x18 +#define R92C_RF_RX_G1 0x1a +#define R92C_RF_RX_G2 0x1b +#define R92C_RF_RX_BB2 0x1c +#define R92C_RF_RX_BB1 0x1d +#define R92C_RF_RCK1 0x1e +#define R92C_RF_RCK2 0x1f +#define R92C_RF_TX_G(i) (0x20 + (i)) +#define R92C_RF_TX_BB1 0x23 +#define R92C_RF_T_METER 0x24 +#define R92C_RF_SYN_G(i) (0x25 + (i)) +#define R92C_RF_RCK_OS 0x30 +#define R92C_RF_TXPA_G(i) (0x31 + (i)) + +/* Bits for R92C_RF_AC. */ +#define R92C_RF_AC_MODE_M 0x70000 +#define R92C_RF_AC_MODE_S 16 +#define R92C_RF_AC_MODE_STANDBY 1 + +/* Bits for R92C_RF_CHNLBW. */ +#define R92C_RF_CHNLBW_CHNL_M 0x003ff +#define R92C_RF_CHNLBW_CHNL_S 0 +#define R92C_RF_CHNLBW_BW20 0x00400 +#define R92C_RF_CHNLBW_LCSTART 0x08000 + + +/* + * CAM entries. + */ +#define R92C_CAM_ENTRY_COUNT 32 + +#define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) +#define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) +#define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) + +/* Bits for R92C_CAM_CTL0(i). */ +#define R92C_CAM_KEYID_M 0x00000003 +#define R92C_CAM_KEYID_S 0 +#define R92C_CAM_ALGO_M 0x0000001c +#define R92C_CAM_ALGO_S 2 +#define R92C_CAM_ALGO_NONE 0 +#define R92C_CAM_ALGO_WEP40 1 +#define R92C_CAM_ALGO_TKIP 2 +#define R92C_CAM_ALGO_AES 4 +#define R92C_CAM_ALGO_WEP104 5 +#define R92C_CAM_VALID 0x00008000 +#define R92C_CAM_MACLO_M 0xffff0000 +#define R92C_CAM_MACLO_S 16 + +/* Rate adaptation modes. */ +#define R92C_RAID_11GN 1 +#define R92C_RAID_11N 3 +#define R92C_RAID_11BG 4 +#define R92C_RAID_11G 5 /* "pure" 11g */ +#define R92C_RAID_11B 6 + + +/* Macros to access unaligned little-endian memory. */ +#define LE_READ_2(x) ((x)[0] | (x)[1] << 8) +#define LE_READ_4(x) ((x)[0] | (x)[1] << 8 | (x)[2] << 16 | (x)[3] << 24) + +/* + * Macros to access subfields in registers. + */ +/* Mask and Shift (getter). */ +#define MS(val, field) \ + (((val) & field##_M) >> field##_S) + +/* Shift and Mask (setter). */ +#define SM(field, val) \ + (((val) << field##_S) & field##_M) + +/* Rewrite. */ +#define RW(var, field, val) \ + (((var) & ~field##_M) | SM(field, val)) + +/* + * Firmware image header. + */ +struct r92c_fw_hdr { + /* QWORD0 */ + uint16_t signature; + uint8_t category; + uint8_t function; + uint16_t version; + uint16_t subversion; + /* QWORD1 */ + uint8_t month; + uint8_t date; + uint8_t hour; + uint8_t minute; + uint16_t ramcodesize; + uint16_t reserved2; + /* QWORD2 */ + uint32_t svnidx; + uint32_t reserved3; + /* QWORD3 */ + uint32_t reserved4; + uint32_t reserved5; +} __packed; + +/* + * Host to firmware commands. + */ +#define R92C_CMD_AP_OFFLOAD 0 +#define R92C_CMD_SET_PWRMODE 1 +#define R92C_CMD_JOINBSS_RPT 2 +#define R92C_CMD_RSVD_PAGE 3 +#define R92C_CMD_RSSI 4 +#define R92C_CMD_RSSI_SETTING 5 +#define R92C_CMD_MACID_CONFIG 6 +#define R92C_CMD_MACID_PS_MODE 7 +#define R92C_CMD_P2P_PS_OFFLOAD 8 +#define R92C_CMD_SELECTIVE_SUSPEND 9 +#define R92C_CMD_FLAG_EXT 0x80 + +/* Structure for R92C_CMD_RSSI_SETTING. */ +struct r92c_fw_cmd_rssi { + uint8_t macid; + uint8_t reserved; + uint8_t pwdb; +} __packed; + +/* Structure for R92C_CMD_MACID_CONFIG. */ +struct r92c_fw_cmd_macid_cfg { + uint32_t mask; + uint8_t macid; +#define URTWN_MACID_BSS 0 +#define URTWN_MACID_BC 4 /* Broadcast. */ +#define URTWN_MACID_VALID 0x80 +} __packed; + +/* + * RTL8192CU ROM image. + */ +struct r92c_rom { + uint16_t id; /* 0x8192 */ + uint8_t reserved1[5]; + uint8_t dbg_sel; + uint16_t reserved2; + uint16_t vid; + uint16_t pid; + uint8_t usb_opt; + uint8_t ep_setting; + uint16_t reserved3; + uint8_t usb_phy; + uint8_t reserved4[3]; + uint8_t macaddr[6]; + uint8_t string[61]; /* "Realtek" */ + uint8_t subcustomer_id; + uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; + uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; + uint8_t ht40_2s_tx_pwr_diff[3]; + uint8_t ht20_tx_pwr_diff[3]; + uint8_t ofdm_tx_pwr_diff[3]; + uint8_t ht40_max_pwr[3]; + uint8_t ht20_max_pwr[3]; + uint8_t xtal_calib; + uint8_t tssi[R92C_MAX_CHAINS]; + uint8_t thermal_meter; + uint8_t rf_opt1; +#define R92C_ROM_RF1_REGULATORY_M 0x07 +#define R92C_ROM_RF1_REGULATORY_S 0 +#define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 +#define R92C_ROM_RF1_BOARD_TYPE_S 5 +#define R92C_BOARD_TYPE_DONGLE 0 +#define R92C_BOARD_TYPE_HIGHPA 1 +#define R92C_BOARD_TYPE_MINICARD 2 +#define R92C_BOARD_TYPE_SOLO 3 +#define R92C_BOARD_TYPE_COMBO 4 + + uint8_t rf_opt2; + uint8_t rf_opt3; + uint8_t rf_opt4; + uint8_t channel_plan; + uint8_t version; + uint8_t curstomer_id; +} __packed; + +/* Rx MAC descriptor. */ +struct r92c_rx_stat { + uint32_t rxdw0; +#define R92C_RXDW0_PKTLEN_M 0x00003fff +#define R92C_RXDW0_PKTLEN_S 0 +#define R92C_RXDW0_CRCERR 0x00004000 +#define R92C_RXDW0_ICVERR 0x00008000 +#define R92C_RXDW0_INFOSZ_M 0x000f0000 +#define R92C_RXDW0_INFOSZ_S 16 +#define R92C_RXDW0_QOS 0x00800000 +#define R92C_RXDW0_SHIFT_M 0x03000000 +#define R92C_RXDW0_SHIFT_S 24 +#define R92C_RXDW0_PHYST 0x04000000 +#define R92C_RXDW0_DECRYPTED 0x08000000 + + uint32_t rxdw1; + uint32_t rxdw2; +#define R92C_RXDW2_PKTCNT_M 0x00ff0000 +#define R92C_RXDW2_PKTCNT_S 16 + + uint32_t rxdw3; +#define R92C_RXDW3_RATE_M 0x0000003f +#define R92C_RXDW3_RATE_S 0 +#define R92C_RXDW3_HT 0x00000040 +#define R92C_RXDW3_HTC 0x00000400 + + uint32_t rxdw4; + uint32_t rxdw5; +} __packed __attribute__((aligned(4))); + +/* Rx PHY descriptor. */ +struct r92c_rx_phystat { + uint32_t phydw0; + uint32_t phydw1; + uint32_t phydw2; + uint32_t phydw3; + uint32_t phydw4; + uint32_t phydw5; + uint32_t phydw6; + uint32_t phydw7; +} __packed __attribute__((aligned(4))); + +/* Rx PHY CCK descriptor. */ +struct r92c_rx_cck { + uint8_t adc_pwdb[4]; + uint8_t sq_rpt; + uint8_t agc_rpt; +} __packed; + +/* Tx MAC descriptor. */ +struct r92c_tx_desc { + uint32_t txdw0; +#define R92C_TXDW0_PKTLEN_M 0x0000ffff +#define R92C_TXDW0_PKTLEN_S 0 +#define R92C_TXDW0_OFFSET_M 0x00ff0000 +#define R92C_TXDW0_OFFSET_S 16 +#define R92C_TXDW0_BMCAST 0x01000000 +#define R92C_TXDW0_LSG 0x04000000 +#define R92C_TXDW0_FSG 0x08000000 +#define R92C_TXDW0_OWN 0x80000000 + + uint32_t txdw1; +#define R92C_TXDW1_MACID_M 0x0000001f +#define R92C_TXDW1_MACID_S 0 +#define R92C_TXDW1_AGGEN 0x00000020 +#define R92C_TXDW1_AGGBK 0x00000040 +#define R92C_TXDW1_QSEL_M 0x00001f00 +#define R92C_TXDW1_QSEL_S 8 +#define R92C_TXDW1_QSEL_BE 0x00 +#define R92C_TXDW1_QSEL_MGNT 0x12 +#define R92C_TXDW1_RAID_M 0x000f0000 +#define R92C_TXDW1_RAID_S 16 +#define R92C_TXDW1_CIPHER_M 0x00c00000 +#define R92C_TXDW1_CIPHER_S 22 +#define R92C_TXDW1_CIPHER_NONE 0 +#define R92C_TXDW1_CIPHER_RC4 1 +#define R92C_TXDW1_CIPHER_AES 3 +#define R92C_TXDW1_PKTOFF_M 0x7c000000 +#define R92C_TXDW1_PKTOFF_S 26 + + uint32_t txdw2; + uint16_t txdw3; + uint16_t txdseq; + + uint32_t txdw4; +#define R92C_TXDW4_RTSRATE_M 0x0000003f +#define R92C_TXDW4_RTSRATE_S 0 +#define R92C_TXDW4_QOS 0x00000040 +#define R92C_TXDW4_HWSEQ 0x00000080 +#define R92C_TXDW4_DRVRATE 0x00000100 +#define R92C_TXDW4_CTS2SELF 0x00000800 +#define R92C_TXDW4_RTSEN 0x00001000 +#define R92C_TXDW4_HWRTSEN 0x00002000 +#define R92C_TXDW4_SCO_M 0x003f0000 +#define R92C_TXDW4_SCO_S 20 +#define R92C_TXDW4_SCO_SCA 1 +#define R92C_TXDW4_SCO_SCB 2 +#define R92C_TXDW4_40MHZ 0x02000000 + + uint32_t txdw5; +#define R92C_TXDW5_DATARATE_M 0x0000003f +#define R92C_TXDW5_DATARATE_S 0 +#define R92C_TXDW5_SGI 0x00000040 +#define R92C_TXDW5_AGGNUM_M 0xff000000 +#define R92C_TXDW5_AGGNUM_S 24 + + uint32_t txdw6; + uint16_t txdsum; + uint16_t pad; +} __packed __attribute__((aligned(4))); diff --exclude=CVS --exclude='.#*' --exclude='obj.*' --exclude='makeBuild*' -uNr src.orig/sys/dev/usb/if_urtwnvar.h src/sys/dev/usb/if_urtwnvar.h --- src.orig/sys/dev/usb/if_urtwnvar.h 1970-01-01 09:00:00.000000000 +0900 +++ src/sys/dev/usb/if_urtwnvar.h 2012-01-30 21:35:20.000000000 +0900 @@ -0,0 +1,177 @@ +/* $NetBSD$ */ +/* $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ */ + +/*- + * Copyright (c) 2010 Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * Driver definitions. + */ +#define URTWN_RX_LIST_COUNT 1 +#define URTWN_TX_LIST_COUNT 8 +#define URTWN_HOST_CMD_RING_COUNT 32 + +#define URTWN_RXBUFSZ (16 * 1024) +#define URTWN_TXBUFSZ (sizeof(struct r92c_tx_desc) + IEEE80211_MAX_LEN + 8) + +#define URTWN_RIDX_COUNT 28 + +#define URTWN_TX_TIMEOUT 5000 /* ms */ + +#define URTWN_LED_LINK 0 +#define URTWN_LED_DATA 1 + +struct urtwn_rx_radiotap_header { + struct ieee80211_radiotap_header wr_ihdr; + uint8_t wr_flags; + uint8_t wr_rate; + uint16_t wr_chan_freq; + uint16_t wr_chan_flags; + uint8_t wr_dbm_antsignal; +} __packed; + +#define URTWN_RX_RADIOTAP_PRESENT \ + (1 << IEEE80211_RADIOTAP_FLAGS | \ + 1 << IEEE80211_RADIOTAP_RATE | \ + 1 << IEEE80211_RADIOTAP_CHANNEL | \ + 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) + +struct urtwn_tx_radiotap_header { + struct ieee80211_radiotap_header wt_ihdr; + uint8_t wt_flags; + uint16_t wt_chan_freq; + uint16_t wt_chan_flags; +} __packed; + +#define URTWN_TX_RADIOTAP_PRESENT \ + (1 << IEEE80211_RADIOTAP_FLAGS | \ + 1 << IEEE80211_RADIOTAP_CHANNEL) + +struct urtwn_softc; + +struct urtwn_rx_data { + struct urtwn_softc *sc; + usbd_xfer_handle xfer; + uint8_t *buf; +}; + +struct urtwn_tx_data { + struct urtwn_softc *sc; + usbd_pipe_handle pipe; + usbd_xfer_handle xfer; + uint8_t *buf; + TAILQ_ENTRY(urtwn_tx_data) next; +}; + +struct urtwn_host_cmd { + void (*cb)(struct urtwn_softc *, void *); + uint8_t data[256]; +}; + +struct urtwn_cmd_newstate { + enum ieee80211_state state; + int arg; +}; + +struct urtwn_host_cmd_ring { + struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT]; + int cur; + int next; + int queued; +}; + +#if 1 /* XXX: sys/net80211/ieee80211.h */ +#define IEEE80211_QOS_ACKPOLICY_BA 0x60 /* Block ACK */ + +#define IEEE80211_HTINFO_2NDCHAN 0x03 /* secondary/ext chan offset */ +#define IEEE80211_HTINFO_2NDCHAN_S 0 +#define IEEE80211_HTINFO_2NDCHAN_NONE 0x00 /* no secondary/ext channel */ +#define IEEE80211_HTINFO_2NDCHAN_ABOVE 0x01 /* above private channel */ +/* NB: 2 is reserved */ +#define IEEE80211_HTINFO_2NDCHAN_BELOW 0x03 /* below primary channel */ +#endif /* XXX: 1 */ + +struct urtwn_softc { + device_t sc_dev; + struct ieee80211com sc_ic; + struct ethercom sc_ec; +#define sc_if sc_ec.ec_if + int (*sc_newstate)(struct ieee80211com *, + enum ieee80211_state, int); + + usbd_device_handle sc_udev; + usbd_interface_handle sc_iface; + u_int sc_flags; +#define URTWN_FLAG_CCK_HIPWR __BIT(0) +#define URTWN_FLAG_ATTACHED __BIT(1) +#define URTWN_FLAG_FWREADY __BIT(2) + int sc_dying; + + struct usb_task sc_task; + callout_t sc_scan_to; + callout_t sc_calib_to; + + kmutex_t sc_task_mtx; + kmutex_t sc_fwcmd_mtx; + kmutex_t sc_tx_mtx; + + usbd_pipe_handle rx_pipe; + usbd_pipe_handle tx_pipe[R92C_MAX_EPOUT]; + int ac2idx[WME_NUM_AC]; + + u_int chip; +#define URTWN_CHIP_92C 0x01 +#define URTWN_CHIP_92C_1T2R 0x02 +#define URTWN_CHIP_UMC 0x04 +#define URTWN_CHIP_UMC_A_CUT 0x08 + + uint8_t board_type; + uint8_t regulatory; + uint8_t pa_setting; + int avg_pwdb; + int thcal_state; + int thcal_lctemp; + int ntxchains; + int nrxchains; + int ledlink; + bool iqk_inited; + + int tx_timer; + + struct urtwn_host_cmd_ring cmdq; + int fwcur; + struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT]; + struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT]; + TAILQ_HEAD(, urtwn_tx_data) tx_free_list; + + struct r92c_rom rom; + + uint32_t rf_chnlbw[R92C_MAX_CHAINS]; + + struct bpf_if * sc_drvbpf; + union { + struct urtwn_rx_radiotap_header th; + uint8_t pad[64]; + } sc_rxtapu; +#define sc_rxtap sc_rxtapu.th + int sc_rxtap_len; + union { + struct urtwn_tx_radiotap_header th; + uint8_t pad[64]; + } sc_txtapu; +#define sc_txtap sc_txtapu.th + int sc_txtap_len; +}; diff --exclude=CVS --exclude='.#*' --exclude='obj.*' --exclude='makeBuild*' -uNr src.orig/sys/dev/usb/usbdevices.config src/sys/dev/usb/usbdevices.config --- src.orig/sys/dev/usb/usbdevices.config 2012-01-17 12:49:20.000000000 +0900 +++ src/sys/dev/usb/usbdevices.config 2012-01-19 23:01:28.000000000 +0900 @@ -116,6 +116,7 @@ ral* at uhub? port ? # Ralink Technology RT25x0 802.11a/b/g rum* at uhub? port ? # Ralink Technology RT2501/RT2601 802.11a/b/g upgt* at uhub? port ? # Intersil PrismGT +urtwn* at uhub? port ? # Realtek RTL8188CU/RTL8192CU 802.11b/g/n zyd* at uhub? port ? # Zydas ZD1211 # Prolific PL2301/PL2302 host-to-host adapter diff --exclude=CVS --exclude='.#*' --exclude='obj.*' --exclude='makeBuild*' -uNr src.orig/share/man/man4/Makefile src/share/man/man4/Makefile --- src.orig/share/man/man4/Makefile 2012-01-22 15:44:31.000000000 +0900 +++ src/share/man/man4/Makefile 2012-01-22 15:51:27.000000000 +0900 @@ -75,7 +75,7 @@ ucycom.4 udav.4 udsbr.4 uftdi.4 ugen.4 ugensa.4 uhci.4 uhid.4 \ uhidev.4 uhmodem.4 uhso.4 uipaq.4 uirda.4 ukbd.4 ukyopon.4 ulpt.4 \ umass.4 umct.4 umidi.4 umodem.4 ums.4 upgt.4 upl.4 uplcom.4 \ - urio.4 url.4 urndis.4 usb.4 uscanner.4 uslsa.4 usscanner.4 \ + urio.4 url.4 urndis.4 urtwn.4 usb.4 uscanner.4 uslsa.4 usscanner.4 \ ustir.4 uthum.4 utoppy.4 uts.4 uvideo.4 uvisor.4 uvscom.4 uyap.4 \ uyurex.4 diff --exclude=CVS --exclude='.#*' --exclude='obj.*' --exclude='makeBuild*' -uNr src.orig/share/man/man4/urtwn.4 src/share/man/man4/urtwn.4 --- src.orig/share/man/man4/urtwn.4 1970-01-01 09:00:00.000000000 +0900 +++ src/share/man/man4/urtwn.4 2012-01-20 05:27:16.000000000 +0900 @@ -0,0 +1,183 @@ +.\" $NetBSD$ +.\" $OpenBSD: urtwn.4,v 1.15 2011/11/26 06:39:33 ckuethe Exp $ +.\" +.\" Copyright (c) 2010 Damien Bergamini +.\" +.\" Permission to use, copy, modify, and distribute this software for any +.\" purpose with or without fee is hereby granted, provided that the above +.\" copyright notice and this permission notice appear in all copies. +.\" +.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +.\" +.Dd $Mdocdate: November 26 2011 $ +.Dt URTWN 4 +.Os +.Sh NAME +.Nm urtwn +.Nd Realtek RTL8188CU/RTL8192CU USB IEEE 802.11b/g/n wireless network device +.Sh SYNOPSIS +.Cd "urtwn* at uhub? port ?" +.Sh DESCRIPTION +The +.Nm +driver supports USB 2.0 wireless network devices based on Realtek +RTL8188CUS, RTL8188CE-VAU, RTL8188RU and RTL8192CU chipsets. +.Pp +The RTL8188CUS is a highly integrated 802.11n adapter that combines +a MAC, a 1T1R capable baseband and an RF in a single chip. +It operates in the 2GHz spectrum only. +The RTL8188RU is a high-power variant of the RTL8188CUS. +The RTL8188CE-VAU is a PCI Express Mini Card adapter that attaches +to the USB interface. +.Pp +The RTL8192CU is a highly integrated multiple-in, multiple-out (MIMO) +802.11n adapter that combines a MAC, a 2T2R capable baseband and an +RF in a single chip. +It operates in the 2GHz spectrum only. +.Pp +These are the modes the +.Nm +driver can operate in: +.Bl -tag -width "IBSS-masterXX" +.It BSS mode +Also known as +.Em infrastructure +mode, this is used when associating with an access point, through +which all traffic passes. +This mode is the default. +.It monitor mode +In this mode the driver is able to receive packets without +associating with an access point. +This disables the internal receive filter and enables the card to +capture packets from networks which it wouldn't normally have access to, +or to scan for access points. +.El +.Pp +The +.Nm +driver can be configured to use +Wired Equivalent Privacy (WEP) or +Wi-Fi Protected Access (WPA-PSK and WPA2-PSK). +WPA is the de facto encryption standard for wireless networks. +It is strongly recommended that WEP +not be used as the sole mechanism +to secure wireless communication, +due to serious weaknesses in it. +.Pp +The +.Nm +driver can be configured at runtime with +.Xr ifconfig 8 +or on boot with +.Xr ifconfig.if 5 . +.Sh FILES +The driver needs at least version 1.1p0 of the following firmware files, +which are loaded when an interface is attached: +.Pp +.Bl -tag -width Ds -offset indent -compact +.It /libdata/firmware/urtwn/urtwn-rtl8192cfwT +.It /libdata/firmware/urtwn/urtwn-rtl8192cfwU +.It /libdata/firmware/urtwn/urtwn-rtl8723fw +.El +.Pp +A prepackaged version of the firmware, designed to be used with +.Xr pkg_add 1 , +can be found at: +.Bd -literal -offset 3n +http://firmware.openbsd.org/firmware/urtwn-firmware-1.1p0.tgz +.Ed +.Sh HARDWARE +The following adapters should work: +.Pp +.Bl -tag -width Ds -offset indent -compact +.It Airlink101 AWLL5088 +.It Aus. Linx AL-9604R1S +.It B-Link BL-LW05-5R +.It Belkin F7D1102 Surf Wireless Micro +.It D-Link DWA-121 +.It D-Link DWA-133 +.It D-Link DWA-135 +.It Digitus DN-7042 +.It Edimax EW-7811Un +.It EDUP EP-N8508 +.It Full River FR-W100NUL +.It Hercules Wireless N USB Pico HWNUp-150 +.It Netgear WNA1000A +.It Planex GW-USEco300 +.It Planex GW-USNano2 +.It Planex GW-USValue-EZ +.It Planex GW-USWExtreme +.It POWCHIP POW-N18 +.It Sitecom WL-365 +.It Solwise NET-WL-UMD-606N +.It TRENDnet TEW-648UBM +.El +.Sh EXAMPLES +The following +.Xr ifconfig.if 5 +example configures urtwn0 to join whatever network is available on boot, +using WEP key +.Dq 0x1deadbeef1 , +channel 11, obtaining an IP address using DHCP: +.Bd -literal -offset indent +dhcp NONE NONE NONE nwkey 0x1deadbeef1 chan 11 +.Ed +.Pp +Configure urtwn0 to join network +.Dq my_net +using WPA with passphrase +.Dq my_passphrase : +.Bd -literal -offset indent +# ifconfig urtwn0 nwid my_net wpakey my_passphrase +.Ed +.Pp +Join an existing BSS network, +.Dq my_net : +.Bd -literal -offset indent +# ifconfig urtwn0 192.168.1.1 netmask 0xffffff00 nwid my_net +.Ed +.Sh DIAGNOSTICS +.Bl -diag +.It "urtwn%d: error %d, could not read firmware %s" +For some reason, the driver was unable to read the microcode file from the +filesystem. +The file might be missing or corrupted. +.It "urtwn%d: device timeout" +A frame dispatched to the hardware for transmission did not complete in time. +The driver will reset the hardware. +This should not happen. +.El +.Sh SEE ALSO +.Xr arp 4 , +.Xr intro 4 , +.Xr netintro 4 , +.Xr usb 4 , +.Xr ifconfig.if 5 , +.Xr ifconfig 8 +.Sh HISTORY +The +.Nm +device driver first appeared in +.Ox 4.9 +and in +.Nx 6.0 . +.Sh AUTHORS +The +.Nm +driver was written by +.An Damien Bergamini Aq damien@openbsd.org +. +.Sh CAVEATS +The +.Nm +driver does not support any of the 802.11n capabilities offered by the +adapters. +Additional work is required in +.Xr ieee80211 9 +before those features can be supported. diff --exclude=CVS --exclude='.#*' --exclude='obj.*' --exclude='makeBuild*' -uNr src.orig/share/man/man4/usb.4 src/share/man/man4/usb.4 --- src.orig/share/man/man4/usb.4 2012-01-22 23:15:43.000000000 +0900 +++ src/share/man/man4/usb.4 2012-01-23 05:02:47.000000000 +0900 @@ -150,6 +150,8 @@ USB Bluetooth dongles .It Xr upgt 4 Conexant/Intersil PrismGT SoftMAC USB 802.11b/g wireless network device +.It Xr urtwn 4 +Realtek RTL8188CU/RTL8192CU 802.11b/g/n wireless network device .It Xr zyd 4 ZyDAS ZD1211/ZD1211B USB IEEE 802.11b/g wireless network device .El --- src.orig/distrib/sets/lists/man/mi 2012-01-22 17:58:13.000000000 +0900 +++ src/distrib/sets/lists/man/mi 2012-01-22 18:07:20.000000000 +0900 @@ -1714,6 +1714,7 @@ ./usr/share/man/cat4/url.0 man-sys-catman .cat ./usr/share/man/cat4/urlphy.0 man-sys-catman .cat ./usr/share/man/cat4/urndis.0 man-sys-catman .cat +./usr/share/man/cat4/urtwn.0 man-sys-catman .cat ./usr/share/man/cat4/usb.0 man-sys-catman .cat ./usr/share/man/cat4/usbtask.0 man-sys-catman .cat ./usr/share/man/cat4/uscanner.0 man-sys-catman .cat @@ -4499,6 +4500,7 @@ ./usr/share/man/html4/url.html man-sys-htmlman html ./usr/share/man/html4/urlphy.html man-sys-htmlman html ./usr/share/man/html4/urndis.html man-sys-htmlman html +./usr/share/man/html4/urtwn.html man-sys-htmlman html ./usr/share/man/html4/usb.html man-sys-htmlman html ./usr/share/man/html4/usbtask.html man-sys-htmlman html ./usr/share/man/html4/uscanner.html man-sys-htmlman html @@ -7211,6 +7213,7 @@ ./usr/share/man/man4/url.4 man-sys-man .man ./usr/share/man/man4/urlphy.4 man-sys-man .man ./usr/share/man/man4/urndis.4 man-sys-man .man +./usr/share/man/man4/urtwn.4 man-sys-man .man ./usr/share/man/man4/usb.4 man-sys-man .man ./usr/share/man/man4/usbtask.4 man-sys-man .man ./usr/share/man/man4/uscanner.4 man-sys-man .man diff --exclude=CVS --exclude='.#*' --exclude='obj.*' --exclude='makeBuild*' -uNr src.orig/etc/mtree/NetBSD.dist.base src/etc/mtree/NetBSD.dist.base --- src.orig/etc/mtree/NetBSD.dist.base 2012-01-28 14:32:49.000000000 +0900 +++ src/etc/mtree/NetBSD.dist.base 2012-01-29 09:33:32.000000000 +0900 @@ -71,6 +71,7 @@ ./libdata/firmware/ral ./libdata/firmware/rum ./libdata/firmware/upgt +./libdata/firmware/urtwn ./libdata/firmware/zyd ./libexec ./libexec/dhcpcd-hooks --- src.orig/distrib/sets/lists/base/mi 2012-01-29 00:10:24.000000000 +0900 +++ src/distrib/sets/lists/base/mi 2012-01-29 09:33:25.000000000 +0900 @@ -182,6 +182,7 @@ ./libdata/firmware/rum/rum-license base-firmware-root ./libdata/firmware/rum/rum-rt2573 base-firmware-root ./libdata/firmware/upgt base-firmware-root +./libdata/firmware/urtwn base-firmware-root ./libdata/firmware/zyd base-firmware-root ./libdata/firmware/zyd/zd1211-licence base-obsolete obsolete ./libdata/firmware/zyd/zd1211-license base-firmware-root